Power management in external memory using PA-CDRAM

International Journal of Embedded Systems

Volumn 3, Issue 1-2, 2007, Pages 65-72

  AbouGhazaleh, Nevine ^a   Childers, Bruce R ^a   Mossé, Daniel ^a   Melhem, Rami G ^a  

^a University of Pittsburgh   (United States)

Author keywords

Cached DRAM; Memory power management

Indexed keywords

DYNAMIC RANDOM ACCESS STORAGE; ENERGY UTILIZATION; POWER MANAGEMENT;

CACHED DRAM; COMPUTING SYSTEM; ENERGY CONSUMER; EXTERNAL MEMORY; LOW ENERGY CONSUMPTION; MEMORY ACCESS; MEMORY POWER MANAGEMENT; REDUCE ENERGY CONSUMPTION;

CACHE MEMORY;

EID: 56349132715     PISSN: 17411068     EISSN: 17411076     Source Type: Journal    
DOI: 10.1504/IJES.2007.016034     Document Type: Article

References (16)

1. Celebican, O., Simunic Rosing, T. and Mooney, V. (2004) 'Energy estimation of peripheral devices in embedded systems', GLSVLSI '04: Proceedings of the 14th ACM Great Lakes Symposium on VLSI, Boston, MA, USA, pp.430-435.
2. Davis, B. (2000) Modern DRAM Architectures, PhD Thesis, University of Michigan, Ann Arbor.
3. Elliott, D., Snelgrove, W. and Stumm, M. (1992) 'Computational RAM: A memory-SIMD Hybrid and its application to DSP', Proceedings of the Custom Integrated Circuits Conference, pp.30.6.1-30.6.4.
4. Gries, M. and Romer, A. (2004) SDRAM and RDRAM Modeling for Simplescalar Simulator, Computer Engineering Research Group, URL: http://www.tik.ee.ethz.ch/~ip3/software/ simplescalar_mem_model.html.
5. Hegde, A., Vijaykrishnan, N., Kandemir, M. and Irwin, M.J. (2003) 'VL-CDRAM: Variable line sized cached DRAMs', Proceedings of the International Symposium on Hardware/Software Codesign and System Synthesis, Newport Beach, CA, USA, pp.132-137.
6. Hsu, W. and Smith, J. (1993) 'Performance of cached DRAM organizations in vector supercomputers', Proceedings of the International Symposium on Computer Architecture, San Diego, California, USA, pp.327-336.
7. Intel Pentium 4 EE Processor (2003) URL: http://www.intel.com.
8. Keitel-Schulz, D. and Wehn, N. (2001) 'Embedded DRAM development: technology, physical design, and application issues', IEEE Transactions on Design and Test of Computers, Vol. 18, No. 3, pp.7-15.
9. Koganti, R. and Kedem, G. (1997) WCDRAM: A Fully Associative Integrated Cached-DRAM with Wide Cache Lines, Technical Report, Department of Computer Science, Duke University, Durham NC, USA.
10. Leung, W. (2005) '[I need more memory: Do I trench or do I stack?', Presentation in the 3rd International System-on-Chip Conference, Mosys Inc., URL: http://www.mosysinc.com/corp/pdf.iiles/pdf/socl005.pdf.
11. Mosys Inc. (2005) 1T-SRAM Products, URL: http://www.mosysinc.com.
12. NEC Embedded DRAM (2005) URL: http://www.necelam.com/edram90/.
13. Rambus Inc. (2005) Products Data Sheets, URL: http://www. rambus.com/products/rdram/documentation.
14. Shivakumar, P. and Jouppi, N. (2001) CACTI 3.0: An Integrated Cache Timing, Power, and Area Model, Technical Report No. 2001.2, Compaq Research Labs, Palo Alto CA, USA.
15. Simplescalar Architectural Simulator (2004) URL: http://www. simplescalar.com.
16. Tomashot, S. (2003) IBM Embedded DRAM Approach, URL: http:// www.ibm.com/chips/techlib/techlib.nsf/products-/Embedded_DRAM.