An improved macro-model for simulation of single electron transistor (SET) using HSPICE

TIC-STH'09: 2009 IEEE Toronto International Conference - Science and Technology for Humanity

Volumn , Issue , 2009, Pages 1000-1004

  Karimian, M ^a   Dousti, M ^a   Pouyan, M ^b   Faez, R ^c  

^a ISLAMIC AZAD UNIVERSITY   (Iran)

^b SHAHED UNIVERSITY   (Iran)

^c SHARIF UNIVERSITY OF TECHNOLOGY   (Iran)

Author keywords

HSPICE; Macro model; Quantizer; SIMON; Single electron transistor (SET); Switched capacitor circuit

Indexed keywords

COMPLICATED CIRCUITS; DELAY TIME; HIGH-SPEED; MACRO-MODEL; QUANTIZERS; SIMULATION RESULT; SWITCHED CAPACITOR CIRCUITS;

CAPACITANCE; CAPACITANCE MEASUREMENT; CAPACITORS; COMPUTER SIMULATION; DELAY CIRCUITS; ELECTRON TRAPS; ELECTRON TUNNELING; ELECTRONS; TECHNOLOGICAL FORECASTING; TEMPERATURE INDICATING CAMERAS; TRANSIENTS; TUNNELING (EXCAVATION);

SINGLE ELECTRON TRANSISTORS;

EID: 77952729425     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/TIC-STH.2009.5444535     Document Type: Conference Paper

References (25)

1. K.K. Likharev, "Single-electron devices and their applications", Proceeding of the IEEE, Volume: 87 Issue: 4, pp.606-632, April 1999.
2. C. Wasshuber, "Computational Single-Electronics", Springer- Verlag, Wien 2001.
3. M. Troudia, Na. Sghaierb, A. Boubakera, A. Souific, A. Kalboussia, "Macro-modeling for the compact simulation of single electron transistor using SIMPLORER",Microelectronics Journal, Volume: 38, pp. 1156-1160, 2007.
4. A. Boubakera, Na. Sghaierb, M. Troudia, A. Kalboussia, N. Babouxc, A. Souific, "A new SIMPLORER model for single-electron transistors", Microelectronics Journal, Volume: 38,pp. 894-899, 2007.
5. M. Sulieman, V. Beiu ," Design and Analysis of SET Circuits: Using MATLAB Modules and SIMON", 4th. IEEE Conference on Nanotechnology, 2004.
6. C. Wasshuber, H. Kosina, and S. Selberherr, "SIMON: A simulator for single-electron tunnel devices and circuits," IEEE Trans. Comp. Aided Design, vol. 16, pp. 937-944, Sep. 1997.
7. M, Saitoh, H. Harata, T. Hiramoto," Room-Temperature Demonstration of Integrated Silicon Single-Electron Transistor Circuits for Current Switching and Analog Pattern Matching", IEEE International Electron Devices Meeting ( IEDM), pp.187-190,2004.
8. Y. L. Wu, S.T. Lin, " An Improved Single-Electron-Transistor Model for SPICE Application", Nanotech, Volume:3,pp. 321-324,2003.
9. A.M. Ionescu, M.J. Declercq, S. Mahapatra, K. Banerjee, J. Gautier," Few Electron Devices: Towards Hybrid CMOS-SET Integrated Circuits", 39th Design Automation Conference, pp. 88-93, June 2002.
10. M.E. Kiziroglou, I. Karafyllidis, "Design and simulation of a nano-electronic single-electron analog to digital converter", Microelectronics Journal, Volume: 34,pp. 785-789, 2003.
11. Y. S. Yu, H. S. Lee, S. W. Hwang, "SPICE Macro-Modeling for the Compact Simulation of Single Electron Circuits", Journal of the Korean Physical Society, Volume: 33, pp. S269-S272, November 1998.
12. F. Zhang, R. Tang, Y.B. Kim," SET-based nano-circuit simulation and design method using HSPICE", Microelectronics Journal, Volume: 36, pp. 741-748, 2005.
13. H. Chaohong, S.D. Cotofana, J. Jianfei ,"Analysis of Analog to Digital Converter Based on Single-Electron Tunneling Transistors", IEEE International Symposium on Circuits and Systems, 2004.
14. K.W. Song, K. R Kim, J. D. Lee, B.G. Park, S.H. Lee, D. H. Kim, "A SPICE Model of Realistic Single-Electron Transistors and Its Application to Multiple-Valued Logic", Journal of the Korean Physical Society, Volume: 44, No. 1, pp. 121-124, January 2004.
15. X. WANG, W. POROD," Single-electron transistor analytic I-V model for SPICE simulations", Superlattices and Microstructures, Volume: 28, No. 5/6, pp. 345-349, 2000.
16. M. A. Kastner, "The single electron transistor and artificial atoms", Ann. Phys. (Leipzig), pp.885 - 894, 2000.
17. G. T. Zardalidis, I. Karafyllidis," Design and simulation of a nanoelectronic single electron 2-4 decoder using a novel simulator", Microelectronics Journal, Volume: 38, pp.381-387, 2007.
18. C. Lageweg, S. Cotofana , S. Vassiliadis, "Buffer Design Trade-Offs for Single Electron Logic Gates", Proceedings of 2005, 5th IEEE Conference on Nanotechnology,Nagoya, Japan, July 2005.
19. S. Mahapatra, K. Banerjee, F. Pegeon, A. M. Ionescu,"A CAD Framework for Co-Design and Analysis of CMOS-SET Hybrid Integrated Circuits", Proceedings of the International Conference on Computer Aided Design (ICCAD'03), pp. 497-502, 2003.
20. Y. S. Yu, Y. I. Jung, J. H. Park," Simulation of Single-Electron/CMOS Hybrid Circuits Using SPICE Macro-modeling", Journal of the Korean Physical Society, Volume: 35, pp. S991-S994, December 1999.
21. T. Pohjola, "Dynamical Properties of Single-Electron Devices and Molecular Magnets", Ph.D. dissertation, Helsinki University of Technology, Finland , 2001.
22. Z.A.K. Durrani, "Coulomb blockade, single-electron transistors and circuits in silicon", Physica E, Volume: 17, pp.572 - 578, 2003.
23. Y. S. Yu, S.W. Hwang, D. Ahn, "Macro-modeling of Single-Electron Transistors for Efficient Circuit Simulation", IEEE Transactions on Electron Devices, Volume: 46, No. 8, pp. 1667-1671, August 1999.
24. C. R. Lageweg, "Single Electron Tunneling Based Arithmetic Computation", Ph.D. dissertation, Delft, The Netherlands, 2004.
25. C. Wasshuber and H. Kosina, "A Single-Electron Device and Circuit Simulator," Superlattices and Microstructures, vol. 21, no. 1, 1997.