Design methodology of variable latency adders with multistage function speculation

Proceedings of the 11th International Symposium on Quality Electronic Design, ISQED 2010

Volumn , Issue , 2010, Pages 824-830

  Liu, Yongpan ^a   Sun, Yinan ^a   Zhu, Yihao ^a   Yang, Huazhong ^a  

^a TSINGHUA UNIVERSITY   (China)

Author keywords

Design methodology; Multistage function speculation; Variable latency adder

Indexed keywords

ANALYTICAL PERFORMANCE; AREA REDUCTION; AVERAGE-CASE; BIT NUMBERS; CIRCUIT DELAYS; DESIGN METHODOLOGY; DESIGN OPTIMIZATION; ERROR RECOVERY MECHANISMS; LINEAR RELATIONSHIPS; LOW AREA; MULTISTAGE FUNCTION SPECULATION; PROCESS VARIATION; TWO STAGE; VOLTAGE FLUCTUATIONS; WORST-CASE FAULTS;

ADDERS; FAULT DETECTION; OPTIMIZATION;

MACHINE DESIGN;

EID: 77952629081     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2010.5450484     Document Type: Conference Paper

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