Gated clock routing minimizing the switched capacitance

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 1998, Pages 692-697

  Oh, Jaewon ^a   Pedram, Massoud ^a  

^a University of Southern California ^*  (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT MODULES; CLOCK TREE; DESIGN OPTION; GATE CONTROL; GATED CLOCKS; IDLE TIME; INTERNAL NODES;

DESIGN; FORESTRY; VLSI CIRCUITS;

CLOCKS;

EID: 0038048284     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.1998.655933     Document Type: Conference Paper

References (6)

1. Mazhar Alidina, José Monteiro, Srinivas Devadas, Abhijit Ghosh, Marios Papaefthymiou, "Precomputation-Based Sequential Logic Optimization for Low Power," IEEE Transactions on VLSI Systems, vol. 2, no. 4, pp. 426-436, December, 1994.
2. Kenneth D. Boese and Adrew B. Kahng, "Zero-Skew Clock Routing Trees With Minimum Wirelength," Proc. IEEE International Conference on ASIC, pp. 1.1.1-1.1.5, 1992.
3. M. Edahiro, "Minimum Path-Length Equi-Distance Routing," Proc. IEEE Asia-Pacific Conf. on Circuits and Systems, pp. 41-46, 1992.
4. Jaewon Oh and Massoud Pedram, "Power Reduction in Microprocessor Chips by Gated Clock Routing," to appear in Asia and South Pacific Design Automation Conference, 1998.
5. Gustavo E. Téllez, Amir Farrahi, Majid Sarrafzadeh, "Activity Driven Clock Design for Low Power Circuits," Proc. International Conference on Computer-Aided Design, pp. 62-65, 1995.
6. R-S Tsay, "Exact zero skew," International Conference on Computer-Aided Design, pp. 336-339, 1991.