PBTI/NBTI-related variability in TB-SOI and DG MOSFETs

IEEE Electron Device Letters

Volumn 31, Issue 5, 2010, Pages 408-410

  Cheng, B ^a   Brown, A R ^a   Roy, S ^a   Asenov, A ^a  

^a UNIVERSITY OF GLASGOW   (United Kingdom)

Author keywords

Double gate (DG); MOSFETs; Positive bias temperature instability negative bias temperature instability (PBTI NBTI); SOI; Statistical variability (SV)

Indexed keywords

3-D NUMERICAL SIMULATION; BIAS TEMPERATURE INSTABILITY; DG MOSFETS; DOUBLE-GATE MOSFETS; LINE EDGE ROUGHNESS; POSITIVE BIAS TEMPERATURES; SILICON ON INSULATOR; STATISTICAL VARIABILITY; THIN BODY;

COMPUTER SIMULATION; ELECTRIC INSULATORS; MOSFET DEVICES; TERBIUM ALLOYS;

GALERKIN METHODS;

EID: 77951878300     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2010.2043812     Document Type: Article

References (11)

1. A. Asenov, S. Roy, R. A. Brown, G. Roy, C. Alexander, C. Riddet, C. Millar, B. Cheng, A. Martinez, N. Seoane, D. Reid, M. F. Bukhori, X. Wang, and U. Kovac, "Advanced simulation of statistical variability and reliability in nano CMOS transistors," IEDM Tech. Dig., p. 1, 2008. [Online]. Available: http://www.itrs.net/
2. J. C. Liao, Y. K. Fang, Y. T. Hou, C. L. Hung, P. F. Hsu, K. C. Lin, K. T. Huang, T. L. Lee, and M. S. Liang, "BTI reliability of dual metal gate CMOSFETs with HF-based high-κ gate dielectrics," in Proc. VLSI-TSA, 2007, pp. 1-2.
3. S. Mitra, "Circuit failure prediction for robust system design in scaled CMOS," in Proc. IEEE IRPS, 2008, pp. 524-531.
4. V. Huard, C. Parthasarathy, C. Guerin, T. Valentin, E. Pion, M. Mammasse, N. Planes, and L. Camus, "NBTI degradation: From transistors to SRAM arrays," in Proc. IEEE 46th Annu. Int. Reliab. Phys. Symp., 2008, pp. 289-300.
5. S. E. Rauch, "Review and reexamination of reliability effects related to NBTI-induced statistical variations," IEEE Trans. Device Mater. Rel., vol.7, no.4, pp. 524-530, Dec. 2007.
6. A. Asenov, G. Slavcheva, A. R. Brown, J. H. Davies, and S. Saini, "Increase in the random dopant induced threshold fluctuations and lowering in sub-100 nm MOSFETs due to quantum effects: A 3-D density gradient simulation study," IEEE Trans. Electron Devices, vol.48, no.4, pp. 722-729, Apr. 2001. (Pubitemid 32372233)
7. B. Cheng, S. Roy, A. R. Brown, C. Millar, and A. Asenov, "Evalution of statistical variability in 32 and 22 nm technology generation LSTP MOSFETs," Solid State Electron., vol.53, no.7, pp. 767-772, Jul. 2009.
8. H. Dadgour, De Vivek, and K. Banerjee, "Statistical modeling of metal-gate work-function variability in emerging device technologies and implications for circuit design," in Proc. Int. Conf. CAD, 2008, pp. 270-277.
9. K. Ohmori, T. Matsuki, D. Ishikawa, T. Morooka, T. Aminaka, Y. Sugita, T. Chikyow, K. Shiraishi, Y. Nara, and K. Yamada, "Impact of additional factors in threshold voltage variability of metal/high-κ gate stacks and its reduction by controlling crystalline structure and grain size in the metal gates," in IEDM Tech. Dig., 2008, pp. 409-412.
10. V. P. Trivedi and J. G. Fossum, "Nanoscale FD/SOI CMOS: Thick or thin BOX?" IEEE Electron Device Lett., vol.26, no.1, pp. 26-28, Jan. 2005.
11. L. Ge, J. G. Fossum, and F. Gamiz, "Mobility enhancement via volume inversion in double-gate MOSFETs," in Proc. IEEE Int. SOI Conf., 2003, pp. 153-154.