-
1
-
-
84937570416
-
-
Hartong, W., Hedrich, L., Barke, E.: On discrete modeling and model checking for nonlinear analog systems. In: Brinksma, E., Larsen, K.G. (eds.) CAV 2002. LNCS, 2404, pp. 401-413. Springer, Heidelberg (2002)
-
Hartong, W., Hedrich, L., Barke, E.: On discrete modeling and model checking for nonlinear analog systems. In: Brinksma, E., Larsen, K.G. (eds.) CAV 2002. LNCS, vol. 2404, pp. 401-413. Springer, Heidelberg (2002)
-
-
-
-
2
-
-
33750910730
-
Verification of analog and mixed-signal circuits using hybrid systems techniques
-
Hu, A.J, Martin, A.K, eds, FMCAD 2004, Springer, Heidelberg
-
Dang, T., Donzé, A., Maler, O.: Verification of analog and mixed-signal circuits using hybrid systems techniques. In: Hu, A.J., Martin, A.K. (eds.) FMCAD 2004. LNCS, vol. 3312, pp. 21-36. Springer, Heidelberg (2004)
-
(2004)
LNCS
, vol.3312
, pp. 21-36
-
-
Dang, T.1
Donzé, A.2
Maler, O.3
-
3
-
-
34047119262
-
Verifying analog oscillator circuits using forward/backward refinement
-
IEEE Computer Society Press, Los Alamitos
-
Frehse, G., Krogh, B.H., Rutenbar, R.A.: Verifying analog oscillator circuits using forward/backward refinement. In: Proc. Design, Automation and Test in Europe (DATE), pp. 257-262. IEEE Computer Society Press, Los Alamitos (2006)
-
(2006)
Proc. Design, Automation and Test in Europe (DATE)
, pp. 257-262
-
-
Frehse, G.1
Krogh, B.H.2
Rutenbar, R.A.3
-
4
-
-
38149133981
-
Verification of analog/mixed-signal circuits using labeled hybrid petri nets
-
IEEE Computer Society Press, Los Alamitos
-
Little, S., Seegmiller, N., Walter, D., Myers, C., Yoneda, T.: Verification of analog/mixed-signal circuits using labeled hybrid petri nets. In: Proc. International Conference on Computer Aided Design (ICCAD), pp. 275-282. IEEE Computer Society Press, Los Alamitos (2006)
-
(2006)
Proc. International Conference on Computer Aided Design (ICCAD)
, pp. 275-282
-
-
Little, S.1
Seegmiller, N.2
Walter, D.3
Myers, C.4
Yoneda, T.5
-
5
-
-
38149014209
-
Symbolic model checking of analog/mixed-signal circuits
-
Walter, D., Little, S., Seegmiller, N., Myers, C.J., Yoneda, T.: Symbolic model checking of analog/mixed-signal circuits. In: Asia and South Pacific Design Automation Conference (ASPDAC), pp. 316-323 (2007)
-
(2007)
Asia and South Pacific Design Automation Conference (ASPDAC)
, pp. 316-323
-
-
Walter, D.1
Little, S.2
Seegmiller, N.3
Myers, C.J.4
Yoneda, T.5
-
6
-
-
38149043392
-
-
Walter, D., Little, S., Myers, C.: Bounded model checking of analog and mixed-signal circuits using an SMT solver. In: Namjoshi, K.S., Yoneda, T., Higashino, T., Okamura, Y. (eds.) ATVA 2007. LNCS, 4762, pp. 66-81. Springer, Heidelberg (2007)
-
Walter, D., Little, S., Myers, C.: Bounded model checking of analog and mixed-signal circuits using an SMT solver. In: Namjoshi, K.S., Yoneda, T., Higashino, T., Okamura, Y. (eds.) ATVA 2007. LNCS, vol. 4762, pp. 66-81. Springer, Heidelberg (2007)
-
-
-
-
7
-
-
38049130498
-
-
Donzé, A., Maler, O.: Systematic simulation using sensitivity analysis. In: Bemporad, A., Bicchi, A., Buttazzo, G. (eds.) HSCC. LNCS, 4416, Springer, Heidelberg (2007)
-
Donzé, A., Maler, O.: Systematic simulation using sensitivity analysis. In: Bemporad, A., Bicchi, A., Buttazzo, G. (eds.) HSCC. LNCS, vol. 4416, Springer, Heidelberg (2007)
-
-
-
-
8
-
-
38149110669
-
-
Dang, T., Nahhal, T.: Randomized simulation of hybrid systems for circuit validation. Technical report, VERIMAG (May 2006)
-
Dang, T., Nahhal, T.: Randomized simulation of hybrid systems for circuit validation. Technical report, VERIMAG (May 2006)
-
-
-
-
9
-
-
33745791548
-
-
Girard, A., Pappas, G.J.: Verification using simulation. In: Hespanha, J.P., Tiwari, A. (eds.) HSCC 2006. LNCS, 3927, pp. 272-286. Springer, Heidelberg (2006)
-
Girard, A., Pappas, G.J.: Verification using simulation. In: Hespanha, J.P., Tiwari, A. (eds.) HSCC 2006. LNCS, vol. 3927, pp. 272-286. Springer, Heidelberg (2006)
-
-
-
-
10
-
-
33750282529
-
Temporal logic verification using simulation
-
Asarin, E, Bouyer, P, eds, FORMATS 2006, Springer, Heidelberg
-
Fainekos, G.E., Girard, A., Pappas, G.J.: Temporal logic verification using simulation. In: Asarin, E., Bouyer, P. (eds.) FORMATS 2006. LNCS, vol. 4202, pp. 171-186. Springer, Heidelberg (2006)
-
(2006)
LNCS
, vol.4202
, pp. 171-186
-
-
Fainekos, G.E.1
Girard, A.2
Pappas, G.J.3
-
11
-
-
27944487131
-
A verification system for transient response of analog circuits using model checking. In: VLSI Design
-
Los Alamitos
-
Dastidar, T.R., Chakrabarti, P.P.: A verification system for transient response of analog circuits using model checking. In: VLSI Design, pp. 195-200. IEEE Computer Society Press, Los Alamitos (2005)
-
(2005)
IEEE Computer Society Press
, pp. 195-200
-
-
Dastidar, T.R.1
Chakrabarti, P.P.2
-
13
-
-
33744779367
-
The case for analog circuit verification
-
Myers, C.J., Harrison, R.R., Walter, D., Seegmiller, N., Little, S.: The case for analog circuit verification. Electronic Notes Theoretical Computer Science 153(3), 53-63 (2006)
-
(2006)
Electronic Notes Theoretical Computer Science
, vol.153
, Issue.3
, pp. 53-63
-
-
Myers, C.J.1
Harrison, R.R.2
Walter, D.3
Seegmiller, N.4
Little, S.5
-
15
-
-
0000050873
-
Hybrid automata: An algorithmic approach to the specification and verification of hybrid systems
-
Grossman, R.L, Ravn, A.P, Rischel, H, Nerode, A, eds, Hybrid Systems, Springer, Heidelberg
-
Alur, R., Courcoubetis, C., Henzinger, T.A., Ho, P.H.: Hybrid automata: An algorithmic approach to the specification and verification of hybrid systems. In: Grossman, R.L., Ravn, A.P., Rischel, H., Nerode, A. (eds.) Hybrid Systems. LNCS, vol. 736, pp. 209-229. Springer, Heidelberg (1993)
-
(1993)
LNCS
, vol.736
, pp. 209-229
-
-
Alur, R.1
Courcoubetis, C.2
Henzinger, T.A.3
Ho, P.H.4
|