The Case for Analog Circuit Verification

Electronic Notes in Theoretical Computer Science

Volumn 153, Issue 3 SPEC. ISS., 2006, Pages 53-63

  Myers, Chris J ^a   Harrison, Reid R ^a   Walter, David ^a   Seegmiller, Nicholas ^a   Little, Scott ^a  

^a Department of Electrical and Computer Engineering   (United States)

Author keywords

Analog circuits; formal verification; hybrid Petri nets

Indexed keywords

COMPUTER SIMULATION; INTEGRATED CIRCUIT LAYOUT; TESTING;

ANALOG CIRCUITS; FORMAL VERIFICATION; HYBRID PETRI NETS;

ANALOG COMPUTERS;

EID: 33744779367     PISSN: 15710661     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.entcs.2006.02.018     Document Type: Article

References (17)

1. Alur R., Courcoubetis C., Henzinger T.A., and Ho P.-H. Hybrid automata: An algorithmic approach to the specification and verification of hybrid systems. Hybrid Systems. Lecture Notes in Computer Science 736 (1993) 209-229
2. Chen H., and Hanisch H.-M. Analysis of hybrid systems based on hybrid net condition/event system model. Discrete Event Dynamic Systems: Theory and Applications 11 (2001) 163-185
3. Christen E., and Bakalar K. VHDL-AMS-a hardware description language for analog and mixed-signal applications. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 46 (1999) 1263-1272
4. Dang, T., A. Donze and O. Maler, Verification of analog and mixed-signal circuits using hybrid systems techniques, in: Formal Methods for Computer Aided Design, 2004
5. David R., and Alla H. On hybrid petri nets. Discrete Event Dynamic Systems: Theory and Applications 11 (2001) 9-40
6. Ghosh, A. and R. Vemuri, Formal verification of synthesized analog designs, in: International Conference on Computer Design, 1999, pp. 40-45
7. Gupta, S., B.H. Krogh and R.A. Rutenbar, Towards formal verification of analog designs, in: International Conference on Computer-Aided Design, 2004, pp. 210-217
8. Hartong, W., L. Hedrich and E. Barke, Model checking algorithms for analog verification, in: Design Automation Conference, 2002, pp. 542-547
9. Hartong, W., L. Hedrich and E. Barke, On discrete modeling and model checking for nonlinear analog systems, in: Computer Aided Verification. 14th International Conference, 2002, pp. 401-413
10. Hedrich, L. and E. Barke, A formal approach to nonlinear analog circuit verification, in: International Conference on Computer-Aided Design, 1995, pp. 123-127
11. Hedrich, L. and E. Barke, A formal approach to verification of linear analog circuits wth parameter tolerances, in: DATE '98: Proceedings of the conference on Design, automation and test in Europe (1998), pp. 649-655
12. Hendricx, S. and L. Claesen, A symbolic core approach to the formal verification of integrated mixed-mode applications, in: European Design and Test Conference, 1997, pp. 432-436
13. IBS Corporation, Industry reports. (2003)
14. Kurshan R.P., and McMillan K.L. Analysis of digital circuits through symbolic reduction. IEEE Transactions on Computer-Aided Design 10 (1991) 1356-1371
15. Little S., Walter D., Seegmiller N., Myers C., and Yoneda T. Verification of analog and mixed-signal circuits using timed hybrid petri nets. Automated Technology for Verification and Analysis. Lecture Notes in Computer Science 3299 (2004) 426-440
16. Salem, A., Semi-formal verification of VHDL-AMS descriptions, in: International Symposium on Circuits and Systems, 2002, pp. 123-127
17. Serrano-Gotarredona T., and Linares-Barranco B. Systematic width-and-length dependent CMOS transistor mismatch characterization and simulation. Analog Integrated Circuits and Signal Processing 21 (1999) 271-296