Symbolic model checking of analog/mixed-signal circuits

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2007, Pages 316-323

  Walter, David ^a   Little, Scott ^a   Seegmiller, Nicholas ^a   Myers, Chris J ^a   Yoneda, Tomohiro ^b  

^a UNIVERSITY OF UTAH   (United States)

^b NATIONAL INSTITUTE OF INFORMATICS   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG VALUES; BINARY DECISION DIAGRAM (BDD); BOOLEAN VARIABLES; CONTINUOUS VARIABLES; DESIGN AUTOMATION CONFERENCE (DAC); DIGITAL VALUES; HARDWARE DESCRIPTION LANGUAGE (VHDL); HYBRID PETRI NET (HPN); SIGNAL CIRCUITS; SOUTH PACIFIC; STATE SPACES; SYMBOLIC MODEL CHECKING; SYSTEM PROPERTIES; TEMPORAL LOGIC FORMULAS; VERIFICATION ALGORITHMS; VHDL AMS;

ALPHA PARTICLE SPECTROMETERS; ASSET MANAGEMENT; BINARY DECISION DIAGRAMS; BOOLEAN ALGEBRA; BOOLEAN FUNCTIONS; COMPUTER AIDED DESIGN; DATA STRUCTURES; DIGITAL INTEGRATED CIRCUITS; FILE ORGANIZATION; FUNCTION EVALUATION; GRAPH THEORY; INDUSTRIAL ENGINEERING; MAPS; MARINE BIOLOGY; MECHANIZATION; MODEL CHECKING; PARTICLE SPECTROMETERS; PETRI NETS; SEPARATION; STATE SPACE METHODS; TEMPORAL LOGIC;

COMPUTER HARDWARE DESCRIPTION LANGUAGES;

EID: 38149014209     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2007.358005     Document Type: Conference Paper

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