A verification system for transient response of analog circuits using model checking

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 2005, Pages 195-200

  Dastidar, Tathagato Rai ^a   Chakrabarti, P P ^b  

^a NATIONAL SEMICONDUCTOR CORPORATION   (United States)

^b INDIAN INSTITUTE OF TECHNOLOGY   (India)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG CIRCUITS; CONVENTIONAL TEMPORAL LOGICS (CTL); FINITE STATE MACHINES (FSM); POLYNOMIAL TIME;

COMPUTER SIMULATION; MATHEMATICAL MODELS; POLYNOMIALS; REAL TIME SYSTEMS; STATE SPACE METHODS; WAVEFORM ANALYSIS;

LOGIC CIRCUITS;

EID: 27944487131     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

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2. J. R. Burch, E. M. Clarke, D. E. Long, K. L. McMillan, D. L. Dill, "Symbolic Model Checking for Sequential Circuit Verification", IEEE Trans. on CAD of IC and Systems, Vol. 13, Issue 4, April 1994, pp 401-424.
3. W. J. McCalla, Fundamentals of Computer-Aided Circuit Simulation, Kluwer Academic Publishers, 1988.
4. W. Hartong, L. Hedrich, E. Barke, "Model Checking Algorithms for Analog Verification", Proc. DAC 2002, 2002, pp 542-547.
5. A. Balivada, Y. Hoskote, J. A. Abraham, "Verification of Transient Response of Linear Analog Circuits", Proc. 13th IEEE VLSI Test Symposium, 1995, pp 42-47.
6. P. Dasgupta, A. Chakrabarti, P. P. Chakrabarti, "Open Computation Tree Logic for Formal Verification of Modules", Proc. ASP-DAC 2002, pp 735-740.
7. A. Chakrabarti, P. Dasgupta, P. P. Chakrabarti, A. Banerjee, "Formal Verification of Module Interfaces against Real Time Specifications", Proc. 39th DAC, 2002, pp 141-145.
8. P. E. Allen, D. R. Holberg, CMOS Analog Circuit Design, Oxford University Press, 1987.
9. "The Spice Page": http://bwrc.eecs.berkeley.edu/Classes/IcBook/ SPICE