-
1
-
-
0024051146
-
Optimum design of IC power/ground nets subject to reliability constraints
-
July
-
S. Chowdhury and M. A. Breuer, "Optimum Design of IC Power/Ground Nets Subject to Reliability Constraints," IEEE Trans. of Computer-Aided Design, vol. 7, no. 7, pp. 787-796, July 1988
-
(1988)
IEEE Trans. of Computer-aided Design
, vol.7
, Issue.7
-
-
Chowdhury, S.1
Breuer, M.A.2
-
2
-
-
0031642709
-
Design and analysis of power distribution networks in PowerPC microprocessors
-
June
-
A. Dharchoudhury et al. "Design and analysis of power distribution networks in PowerPC microprocessors," Proc. DAC, pp.738-743, June 1998.
-
(1998)
Proc. DAC
, pp. 738-743
-
-
Dharchoudhury, A.1
-
3
-
-
0024888985
-
Automatic sizing of power/ground (P/G) networks in VLSI
-
June
-
R. Dutta and M. Marek-Sadowska, "Automatic sizing of power/ground (P/G) networks in VLSI," Proc. DAC. pp.783-786, June 1989.
-
(1989)
Proc. DAC.
, pp. 783-786
-
-
Dutta, R.1
Marek-Sadowska, M.2
-
4
-
-
0026998546
-
Topology optimization techniques for power/ground networks in VLSI
-
K. H. Erhard, F. M. Johannes, R. Dachauer, "Topology Optimization Techniques for Power/Ground Networks in VLSI," Proc. EURO-DAC, pp362-367, 1992.
-
(1992)
Proc. EURO-DAC
, pp. 362-367
-
-
Erhard, K.H.1
Johannes, F.M.2
Dachauer, R.3
-
5
-
-
84949760157
-
Integrated power supply planning and floorplannina
-
I. M. Liu, H. M. Chen, T. L. Chou, Aziz, A., and Wong, D. F., "Integrated Power Supply Planning and Floorplannina," Proc. ASP-DAC. pp589-594, 2001
-
(2001)
Proc. ASP-DAC
, pp. 589-594
-
-
Liu, I.M.1
Chen, H.M.2
Chou, T.L.3
Aziz, A.4
Wong, D.F.5
-
6
-
-
0027004894
-
Power and ground network optimization
-
T. Mitsuhashi and E. S. Kuh, "Power and ground network optimization," Proc. DAC, pp. 524-529, 1992.
-
(1992)
Proc. DAC
, pp. 524-529
-
-
Mitsuhashi, T.1
Kuh, E.S.2
-
7
-
-
0024131339
-
"Analyzing power supply networks using Ariel
-
June
-
D. Stark and M. Horowitz. "Analyzing power supply networks using Ariel," Proc. Proc. DAC. pp.460-464, June 1988.
-
(1988)
Proc. Proc. DAC
, pp. 460-464
-
-
Stark, D.1
Horowitz, M.2
-
8
-
-
0025387830
-
Techniques for calculating currents and voltages in VLSI power supply networks
-
February
-
D. Stark and M. Horowitz, "Techniques for Calculating Currents and Voltages in VLSI Power Supply Networks," IEEE Tran. of Computer-Aided Design, vol. 9. no. 2. pp. 126-132. February 1990.
-
(1990)
IEEE Tran. of Computer-aided Design
, vol.9
, Issue.2
, pp. 126-132
-
-
Stark, D.1
Horowitz, M.2
-
9
-
-
0034483875
-
Fast analysis and optimization of power/ground networks
-
H. Su, K. H. Gala and S. Sapatnekar. "Fast Analysis and Optimization of Power/Ground Networks," Proc. ICCAD. pp.477-480, 2000.
-
(2000)
Proc. ICCAD
, pp. 477-480
-
-
Su, H.1
Gala, K.H.2
Sapatnekar, S.3
-
10
-
-
0032643254
-
Reliability-constrained area optimization of VLSI power/ground networks via sequence of linear programming
-
X. Tan, C.-J. R. Shi, D. Lungeanu, J.-C. Lee, and L.-P. Yuan, "Reliability-Constrained Area Optimization of VLSI Power/Ground Networks Via Sequence of Linear Programming" Proc. DAC, pp.78-83, 1999.
-
(1999)
Proc. DAC
, pp. 78-83
-
-
Tan, X.1
Shi, C.-J.R.2
Lungeanu, D.3
Lee, J.-C.4
Yuan, L.-P.5
-
11
-
-
0034853864
-
Fast power/ground network optimization based on equivalent circuit modeling
-
X. Tan and C.-J. R. Shi, "Fast Power/Ground Network Optimization Based on Equivalent Circuit Modeling," Proc. DAC, pp550-554, 2001.
-
(2001)
Proc. DAC
, pp. 550-554
-
-
Tan, X.1
Shi, C.-J.R.2
-
12
-
-
0032690819
-
A floorplan-based planning methodology for power and clock distribution in ASICs
-
J. S. Yim, S. O. Bae, and C. M. Kyung, "A Floorplan-Based Planning Methodology for Power and Clock Distribution in ASICs." Proc. DAC, pp. 766-771, 1999.
-
(1999)
Proc. DAC
, pp. 766-771
-
-
Yim, J.S.1
Bae, S.O.2
Kyung, C.M.3
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