Programmable motion estimation architecture

2009 16th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2009

Volumn , Issue , 2009, Pages 323-326

  Drolapas, Anargyros ^a   Lentaris, George ^a   Reisis, Dionysios ^a  

^a UNIVERSITY OF ATHENS   (Greece)

Author keywords

[No Author keywords available]

Indexed keywords

BLOCK MATCHING; COMPILE TIME; FPGA IMPLEMENTATIONS; HARDWARE COST; INSTRUCTION SET; NUMBER OF CYCLES; PARALLEL MEMORY; REAL-TIME MOTION; SEARCH PROCESS; SPECULATIVE EXECUTION; SUB PIXELS;

DIGITAL TELEVISION; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); PIXELS; TELEVISION BROADCASTING;

MOTION ESTIMATION;

EID: 77951456508     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICECS.2009.5411005     Document Type: Conference Paper

References (10)

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