A quarter pel full search block motion estimation architecture for H.264/AVC

IEEE International Conference on Multimedia and Expo, ICME 2005

Volumn 2005, Issue , 2005, Pages 414-417

  Rahman, Choudhury A ^a   Badawy, Wael ^a  

^a UNIVERSITY OF CALGARY   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

BLOCK CODES; COMPUTER SIMULATION; FIELD PROGRAMMABLE GATE ARRAYS; IMAGE CODING; REAL TIME SYSTEMS; SOFTWARE PROTOTYPING; VECTORS;

CLOCK SPEED; GIF FRAME SEQUENCES; MOTION VECTORS; VERILOG HDL;

MOTION ESTIMATION;

EID: 33750567103     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICME.2005.1521448     Document Type: Conference Paper

References (6)

1. "Draft ITU-T Recommendation and Final Draft International Standard of Joint Video Specification (ITU-T Rec. H.264 | ISO/IEC 14496-10 AVC)," in Joint Video Team (JVT) of ISO/IEC MPEG and ITU-T VCEG, JVT-G050r1, May 2003.
2. T. Wiegand, G. J. Sullivan, G. Bjntegaard, and A. Luthra, "Overview of the H.264/AVC video coding standard," IEEE Transactions on Circuits and Systems for Video Technology, vol. 13, no. 7, pp. 560-576, July 2003.
3. "Fast integer pel and fractional pel motion estimation for AVC," in Joint Video Team (JVT) of ISO/IEC MPEG and ITU-T VCEG, JVT-F016, December 2002.
4. Y. W. Huang et. al., "Hardware architecture design for variable block size motion estimation in MPEG-4 AVC/JVT/ITU-T H.264," Proceedings of the 2003 International Symposium on CAS, ISCAS '03, pp. II-796-II-799, May 2003.
5. S. Y. Yap and J. V. McCanny, "A VLSI architecture for variable block size video motion estimation," IEEE Transactions on CAS II, vol. 51, no. 7, July 2004.
6. P. Kuhn, Algorithms, Complexity Analysis and VLSI Architectures for MPEG-4 Motion Estimation, Kluwer Academic Publishers, Boston, 1999.