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Volumn 32, Issue 2, 2008, Pages 68-78

Integer-pixel motion estimation H.264/AVC accelerator architecture with optimal memory management

Author keywords

Image processing; Memory management; Motion estimation; Video coding

Indexed keywords

DIGITAL IMAGE STORAGE; IMAGE CODING; INTEGER PROGRAMMING; MOTION ESTIMATION; OPTIMAL CONTROL SYSTEMS; PIXELS;

EID: 43249093693     PISSN: 01419331     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.micpro.2007.06.002     Document Type: Article
Times cited : (14)

References (13)
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    • ITU-T Video Coding Experts Group (VCEG), ISO/IEC Moving Picture Experts Group (MPEG), ITU-T Rec. H.264/AVC {divides} ISO/IEC International Standard ISO/IEC 14496-10 Video Coding for Generic Audiovisual Services, Version 4, March 2005.
  • 3
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    • H.264 Reference Software Version JM10.1. Available from: , May 2004.
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    • Analysis and architecture design of variable block-size motion estimation for H.264/AVC
    • Chen C.Y., Chien S.Y., Huang Y.W., Chen T.C., Wang T.C., and Chen L.G. Analysis and architecture design of variable block-size motion estimation for H.264/AVC. IEEE Trans. Circuits Syst. 53 2 (2006) 578-593
    • (2006) IEEE Trans. Circuits Syst. , vol.53 , Issue.2 , pp. 578-593
    • Chen, C.Y.1    Chien, S.Y.2    Huang, Y.W.3    Chen, T.C.4    Wang, T.C.5    Chen, L.G.6
  • 8
    • 0038421877 scopus 로고    scopus 로고
    • Y.W. Huang, T.C. Wang, B.Y. Hsieh, L.G. Chen, Hardware architecture design for variable block size motion estimation in MPEG-4 AVC/JVT/ITU-T H.264, IEEE Int. Symp. Circuits Syst. 2 (2003) 796-799.
    • Y.W. Huang, T.C. Wang, B.Y. Hsieh, L.G. Chen, Hardware architecture design for variable block size motion estimation in MPEG-4 AVC/JVT/ITU-T H.264, IEEE Int. Symp. Circuits Syst. 2 (2003) 796-799.
  • 9
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    • Parameterizable VLSI architectures for the full-search block-matching algorithm
    • De Vos L., and Stegherr M. Parameterizable VLSI architectures for the full-search block-matching algorithm. IEEE Trans. Circuits Syst. 36 10 (1989) 1309-1316
    • (1989) IEEE Trans. Circuits Syst. , vol.36 , Issue.10 , pp. 1309-1316
    • De Vos, L.1    Stegherr, M.2
  • 10
    • 0024753317 scopus 로고
    • Array architectures for block matching algorithms
    • Komarek T., and Pirsch P. Array architectures for block matching algorithms. IEEE Trans. Circuits Syst. 36 (1989) 1301-1308
    • (1989) IEEE Trans. Circuits Syst. , vol.36 , pp. 1301-1308
    • Komarek, T.1    Pirsch, P.2
  • 11
    • 0036995762 scopus 로고    scopus 로고
    • Efficient and configurable full-search block-matching processors
    • Roma N., and Sousa L. Efficient and configurable full-search block-matching processors. IEEE Trans. Circuits Systems Video Technol. 12 12 (2002) 1160-1167
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    • L. Zhang, W. Gao, Improved FFSBM algorithm and its VLSI architecture for variable block size motion estimation of H.264, IEEE Int. Symp. Intell. Signal Process. Commun. Syst. (2005) 445-448.
    • L. Zhang, W. Gao, Improved FFSBM algorithm and its VLSI architecture for variable block size motion estimation of H.264, IEEE Int. Symp. Intell. Signal Process. Commun. Syst. (2005) 445-448.
  • 13
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    • T.C. Chen, Y.W. Huang, L.G. Chen, Analysis and design of macroblock pipelining for H.264/AVC VLSI architecture, IEEE Int. Symp. Circuits Syst. 2 (2004) 273-276.
    • T.C. Chen, Y.W. Huang, L.G. Chen, Analysis and design of macroblock pipelining for H.264/AVC VLSI architecture, IEEE Int. Symp. Circuits Syst. 2 (2004) 273-276.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.