A configurable and programmable motion estimation processor for the H.264 video codec

Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL

Volumn , Issue , 2008, Pages 149-154

  Nunez Yanez, Jose Luis ^a   Eddie, Hung ^a   Chouliaras, Vassilios ^b  

^a UNIVERSITY OF BRISTOL   (United Kingdom)

^b LOUGHBOROUGH UNIVERSITY   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; APPLICATIONS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); IMAGE CODING; MOTION PICTURE EXPERTS GROUP STANDARDS; PROGRAMMING THEORY; VISUAL COMMUNICATION;

APPLICATION SPECIFIC INSTRUCTION SET PROCESSORS; BLOCK MATCHING MOTION ESTIMATIONS; COMPILE TIMES; CONFIGURABILITY; CONFIGURABLE; EXECUTION UNITS; FPGA IMPLEMENTATIONS; H.264 VIDEO CODECS; H.264 VIDEO CODING; HIGH DEFINITIONS; INSTRUCTION SETS; MICROARCHITECTURE; MOTION ESTIMATION PROCESSORS; PERFORMANCE REQUIREMENTS;

MOTION ESTIMATION;

EID: 54949107391     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2008.4629923     Document Type: Conference Paper

References (10)

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