SCOPUS 정보 검색 플랫폼

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2008, Pages 568-573

A current source model for CMOS logic cells considering multiple input switching and stack effect

(4) Amelifard, Behnam a Hatami, Safar a Fatemi, Hanif a Pedram, Massoud a

a University of Southern California ^* (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHARACTERIZATION PROCEDURES; CMOS LOGIC; CMOS LOGIC CELLS; CURRENT SOURCE MODEL; LOGIC CELLS; MULTIPLE INPUTS; MULTIPLE-INPUT SWITCHING; NODE VOLTAGES; OUTPUT WAVE FORM; STACK EFFECTS;

CELLULAR RADIO SYSTEMS; INDUSTRIAL ENGINEERING; LOGIC DEVICES; TESTING; TIMING CIRCUITS; VLSI CIRCUITS; VOLTAGE CONTROL;

LOGIC CIRCUITS;

EID: 49749118274 PISSN: 15301591 EISSN: None Source Type: Conference Proceeding
DOI: 10.1109/DATE.2008.4484737 Document Type: Conference Paper

Times cited : (26)

References (8)

1
- 0036810756
- Slope propagation in static timing analysis
- D. Blaauw, V. Zolotov, and S. Sundareswaran, "Slope propagation in static timing analysis," IEEE Trans. Computer Aided-Design of Integrated Circuits & Systems., vol. 21, no. 10, pp. 1180-1195, 2002.
- (2002) IEEE Trans. Computer Aided-Design of Integrated Circuits & Systems , vol.21 , Issue.10 , pp. 1180-1195
- Blaauw, D.¹ Zolotov, V.² Sundareswaran, S.³

2
- 0041633843
- Blade and razor: Cell and interconnect delay analysis using current-based models
- J. F. Croix and D.F. Wong, "Blade and razor: cell and interconnect delay analysis using current-based models," in Proc. Design Automation Conference, pp. 386-389, 2003.
- (2003) Proc. Design Automation Conference , pp. 386-389
- Croix, J.F.¹ Wong, D.F.²

3
- 16244373361
- A robust cell-level crosstalk delay change analysis
- I. Keller, K. Tseng, and N. Verghese, "A robust cell-level crosstalk delay change analysis," in Proc. of International Conference on Computer Aided Design, pp.147-154, 2004.
- (2004) Proc. of International Conference on Computer Aided Design , pp. 147-154
- Keller, I.¹ Tseng, K.² Verghese, N.³

4
- 33748535745
- Waveform independent gate models for accurate timing analysis
- P. Li and E. Acar, "Waveform independent gate models for accurate timing analysis", in Proc. International Conference on Computer Design, pp. 363-365, 2005.
- (2005) Proc. International Conference on Computer Design , pp. 363-365
- Li, P.¹ Acar, E.²

5
- 34547217038
- Statistical logic cell delay analysis using a current-based model
- H. Fatemi, S. Nazarian, and M. Pedram, "Statistical logic cell delay analysis using a current-based model," in Proc. Design Automation Conference, pp. 253-256, 2006.
- (2006) Proc. Design Automation Conference , pp. 253-256
- Fatemi, H.¹ Nazarian, S.² Pedram, M.³

6
- 0034848148
- A new gate delay model for simultaneous switching and its applications
- L.-C. Chen, S. K. Gupta, and M. A. Breuer, "A new gate delay model for simultaneous switching and its applications," in Proc. Design Automation Conference, pp. 289-294, 2001.
- (2001) Proc. Design Automation Conference , pp. 289-294
- Chen, L.-C.¹ Gupta, S.K.² Breuer, M.A.³

7
- 34547176412
- A multi-port current source model for multiple-input switching effects in CMOS library cells
- C. Amin, C. Kashyap, N. Menezes, K. Killpack, and E. Chiprout, "A multi-port current source model for multiple-input switching effects in CMOS library cells," in Proc. Design Automation Conference, pp. 247-252, 2006.
- (2006) Proc. Design Automation Conference , pp. 247-252
- Amin, C.¹ Kashyap, C.² Menezes, N.³ Killpack, K.⁴ Chiprout, E.⁵

8
- 49749121964
- http://www.synopsys.com/products/mixedsignal/hspice/hspice.html

* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.