Transistor level gate modeling for accurate and fast timing, noise, and power analysis

Proceedings - Design Automation Conference

Volumn , Issue , 2008, Pages 456-461

  Raja, S ^a   Varadi, F ^a   Becer, M ^a   Geada, J ^a  

^a CLK Design Automation   (United States)

Author keywords

Crosstalk; Gate modeling; Multi threaded; Statistical; Timing

Indexed keywords

CROSSTALK; GATE MODELING; MULTI THREADED; STATISTICAL; TIMING;

ANALOG TO DIGITAL CONVERSION; CELLS; COMPUTER AIDED DESIGN; COMPUTER NETWORKS; DIGITAL INTEGRATED CIRCUITS; INDUSTRIAL ENGINEERING; STORM SEWERS; SWITCHING CIRCUITS; SYNTHETIC APERTURES; TABLE LOOKUP; TIME MEASUREMENT;

MODAL ANALYSIS;

EID: 51649088243     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DAC.2008.4555861     Document Type: Conference Paper

References (16)

1. F. Dartu, N. Menezes, and L.T. Pileggi "Performance computation for precharacterized CMOS gates with RC loads," In IEEE Transactions on CAD, vol. 15, no. 5, pp. 544-553, May 1996.
2. Composite Current Source, Synopsys 2005, "CCS timing white paper," In http://www.synopsys.com/products/solutions/galaxy/ccs/ cc_source.html
3. Cadence Technical Paper, 2005 "Delay calculation meets the nanometer era," In http://www.cadence.com/products/digital_ic/tech_info.aspx
4. BSIM4 Home Page In http://www-device.eecs.berkeley.edu/bsim.3/bsim4. hml
5. "PathMill: Transistor-level static timing analysis," In http://www.synopsys.com/products/analysis/pathrnill_ds.pdf
6. J.F. Croix, and D.F. Wong "Blade and Razor: Cell and interconnect delay analysis using current-based models," In Proceedings of DAC 2003, pp. 386-389, June 2003
7. E. Ladan-Mozes, and N. Shavit "An optimistic approach to lock-free FIFO queues," In Proceedings of International Conference on Distributed Computing, 2004
8. R. Levy, D. Blaauw, G. Braca, A. Dasgupta, A. Grinshpon, C. Oh, S. Sirichotiyakul, and V. Zolotov "Clarinet: A noise analysis tool for deep submicron design," In Proceedings of DAC 2000, pp. 233-238, June 2000
9. I. Keller, K. Tseng, and N. Verghese "A robust cell-level crosstalk delay change analysis," In Proceedings of ICCAD, pp. 147-154, November 2004
10. C. Amin, C. Kashyap, N. Menezes, K. Killpack, and E. Chiprout "A multi-port current source model for multiple-input switching effects in CMOS library cells," In Proceedings of DAC 2006, pp. 247-252, Jun 2006
11. C. Kashyap, C. Amin, N. Menezes, and E. Chiprout "A nonlinear cell macromodel for digital applications," In Proceedings of ICCAD 2007, pp. 678-685, Nov. 2007
12. A. Odabasioglu, M. Celik, and L. T. Pileggi "PRIMA: Passive reduced-order interconnect macromodeling algorithm," In Proceedings of ICCAD 1997, pp. 58-65, Nov. 1997
13. C. Visweswariah, K. Ravindran, K. Kalafala, S. G. Walker, and S. Narayan "First-order incremental block-based statistical timing analysis," In Proceedings of DAC 2004, pp. 331-336, Jun 2004
14. A. Agarwal, D. Blaauw, and V. Zolotov "Statistical timing analysis for intra-die process variations with spatial correlations," In Proceedings of ICCAD 2003, pp. 900-907, Nov. 2003
15. T. Shima, T. Sugawara, S. Moriyama, and H. Yamada "Three-dimensional table look-up MOSFET model for precise circuit simulation," In IEEE Journal on Solid State Circuits, vol. SC-17, no. 3, June 1982
16. D. Nadezhin, et.al "SOI transistor model for fast transient simulation," In Proceedings of ICCAD, pp. 120-127, November 2003