Low-power and error coding for network-on-chip traffic

Proceedings - Norchip

Volumn , Issue , 2004, Pages 20-23

  Vitkovski, Arseni ^a   Haukilahti, Raimo ^a   Jantsch, Axel ^a   Nilsson, Erland ^a  

^a ROYAL INSTITUTE OF TECHNOLOGY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

CODES (STANDARDS); COMPUTER SIMULATION; CROSSTALK; NETWORKS (CIRCUITS); RELIABILITY; ROUTERS; SPURIOUS SIGNAL NOISE; SWITCHING NETWORKS;

ERROR CODING; NETWORK-ON-CHIP TRAFFIC; ON-CHIP INTERCONNECTS; SHARED BUSES;

MICROPROCESSOR CHIPS;

EID: 21244460341     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (17)

1. A. Jantsch and H. Tenhunen, "Networks on Chip", Kluwer Academic Publishers, 2003.
2. Claudia Kretzschmar, Andre K. Nieuwland, Dietmar Muller, "Why Transition Coding for Power Minimization of on-Chip Buses does not work", IEEE, 2004.
3. D.L. Liu and C. Svensson, "Power consumption estimation in CMOS VLSI chips", IEEE Journal SSC, volume 29, issue 6, pp. 663-670, June 1994.
4. Dinesh Pamunuwa, "Modelling and Analysis of Interconnects for Deep Submicron Systems-on-Chip", Doctoral Thesis, Royal Institute of Technology, Stockholm, Sweden, 2003.
5. Erland Nilsson, "Design and Implementation of a hot-potato Switch in a Network on Chip", Master Thesis, IMIT/LECS 2002-11.
6. Erland Nilsson, Johnny Öberg, "Reducing Power and Latency in 2-D Mesh NoCs Globally Pseudochronous Locally Synchronous Clocking".
7. Heiko Zimmer, Axel Jantsch, "A Fault Model Notation and Error-Control Scheme for Switch-to-Switch Buses in a Network-on-Chip", CODES+ISSS'03, October 1-3, 2003, Newport Beach, California, USA.
8. International Technology Roadmap for Semiconductors, 2003 Edition, http://public.itrs.net/Files/2003ITRS/Home2003.htm.
9. Luca Benini, Giovanni De Michelli, Enrico Macii, and Massimo Poncino, "Power Optimization of Core-Based Systems by Address Bus Encoding", IEEE, 1998.
10. Mehesh Mamidipaka, Dan Hirschberg, and Nikil Dutt, "Low Power Address Encoding using Self-Organizing Lists", ISLPED'01, August 6-7, 2001, Huntington Beach, California, USA.
11. Praveen Vellanki, et al., "Quality-of-Service end Error Control Techniques for Network-on-Chip Architectures", GLSVLSI'04, April 26-28, 2004, Boston, Massachusetts, USA.
12. Ravindra Jejurikar, Cristiano Pereira, and Rajesh K. Gupta, "Leakage Aware Dynamic Voltage Scaling for Real Time Embedded Systems", CECS Technical Report #03-35, November 2003.
13. Robert Siegmund, Claudia Kretzschmar, Dietmar Muller, "Adaptive Partial Businvert Encoding for Power Efficient Data Transfer over Wide System Buses", SBCCI 2000, Manaus, Brasil.
14. Shashi Kumar, Axel Jantsch, Juha-Pekka Soininen, et al., "A Network on Chip Architecture and Design Methodology", ISVLSI'02, 2002.
15. Siu-Kei Wong, Chi-Ying Tsui, "Re-configurable Bus Encoding Scheme for Reducing Power Consumption of the Cross Coupling Capacitance for Deep Sub-micron Instruction Bus", IEEE, 2004.
16. Terry Tao Ye, Luca Benini and Giovanni De Micheli, "Analysis of Power Consumption on Switch Fabrics in Network Routers", DAC 2002, June 10-14, 2002, New Orleans, Louisiana, USA.
17. Vijay Ragnunathan, et al., "A Survey of Techniques for Energy Efficient On-Chip Communication"", DAC 2003, June 2-6, 2003, Anaheim, California, USA.