SCOPUS 정보 검색 플랫폼

Proceedings of the Electronic Packaging Technology Conference, EPTC

Volumn , Issue , 2009, Pages 191-196

Structure and process development of wafer level embedded SiP (system in package) for mobile applications

(3) Jung, Gi Jo a Jeon, Byoung Yool a Kang, In Soo a

a NEPES Corporation (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

BALL MOUNTING; BOARD-LEVEL; BOARD-LEVEL RELIABILITY; DIE SIZE; FEASIBILITY TESTS; FLIP-CHIP BONDING; GAME CONSOLES; LOW COSTS; MAXIMUM STRESS; MOBILE APPLICATIONS; MOLD COMPOUNDS; MOLD MATERIALS; MULTI-FUNCTIONS; PACKAGE LEVELS; PACKAGE SIZE; PORTABLE PRODUCTS; PROCESS DEVELOPMENT; RELIABILITY TEST; SEMICONDUCTOR PACKAGES; SMALL SIZE; STACKED DIE; STRESS SIMULATIONS; SYSTEM IN PACKAGE; TEST VEHICLE; WAFER LEVEL;

CAMERAS; CHIP SCALE PACKAGES; DIELECTRIC MATERIALS; DIES; ELECTRIC BATTERIES; FABRICATION; FLIP CHIP DEVICES; HIGH TEMPERATURE SUPERCONDUCTORS; INTERNET PROTOCOLS; MOLDS; PACKAGING; RELIABILITY; TECHNOLOGY; TELECOMMUNICATION EQUIPMENT; TESTING; THERMAL CONDUCTIVITY; WAFER BONDING;

SILICON WAFERS;

EID: 77950928428 PISSN: None EISSN: None Source Type: Conference Proceeding
DOI: 10.1109/EPTC.2009.5416553 Document Type: Conference Paper

Times cited : (16)

References (8)

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2
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- Brumbauer, M.¹ Firgut, E.²

3
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- Keser, B.¹ Amrine, C.²

4
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5
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6
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7
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- Kumar, A.¹ Dingwei, X.²

8
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.