Embedded wafer level packages with laterally placed and vertically stacked thin dies

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2009, Pages 1537-1543

  Sharma, Gaurav ^a   Rao, Vempati Srinivas ^a   Kumar, Aditya ^a   Su, Nandar ^a   Ying, Lim ^a   Houe, Khong Chee ^a   Lim, Sharon ^a   Sekhar, Vasarla Nagendra ^a   Rajoo, Ranjan ^a   Kripesh, Vaidyanathan ^a   Lau, John H ^b  

^a INSTITUTE OF MICROELECTRONICS   (Singapore)

^b HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

Author keywords

[No Author keywords available]

Indexed keywords

3D STACKING; ACCELERATED STRESS TESTING; AIR-TO-AIR THERMAL CYCLING; BOARD-LEVEL; DIE STACKING; DROP TEST RELIABILITY; EMBEDDED WAFER LEVEL PACKAGES; HIGH RESISTIVITY SILICON; KEY PROCESS; LOW TEMPERATURES; MECHANICAL RELIABILITY; MOISTURE SENSITIVITY LEVEL; MULTI-CHIP; PROCESSING TEMPERATURE; Q-FACTORS; SOLDER BALLS; THERMOMECHANICAL SIMULATION; WAFER LEVEL PACKAGE;

DIES; ELECTRONIC EQUIPMENT TESTING; PROCESSING; SILICON WAFERS; SOLDERING; THERMOMECHANICAL TREATMENT; THIN FILM DEVICES; THIN FILMS;

COMPRESSION MOLDING;

EID: 70349666681     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2009.5074217     Document Type: Conference Paper

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