Chip in Wafer for integrated System

10th Electronics Packaging Technology Conference, EPTC 2008

Volumn , Issue , 2008, Pages 999-1004

  Souriau, Jean Charles ^a   Faivre, Marie Emmanuelle ^a   Sillon, Nicolas ^a  

^a CEA LETI   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRONIC EQUIPMENT MANUFACTURE; INTEGRATED OPTICS; INTERNET PROTOCOLS; SEMICONDUCTING SILICON COMPOUNDS; SILICON WAFERS; TECHNOLOGY;

ABOVE IC PROCESS; CHIP INTEGRATIONS; CRITICAL ISSUES; DRIVING FORCES; INTEGRATED SYSTEMS; KNOWN-GOOD DIES; NEW SYSTEMS; ON WAFERS; PASSIVE INTEGRATIONS; SYSTEM INTEGRATIONS; WAFER LEVELS;

CHIP SCALE PACKAGES;

EID: 63049089617     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EPTC.2008.4763560     Document Type: Conference Paper

References (8)

1. W. Koh, "System in Package (SiP) Technology Applications "6th International Conference on Electronic Packaging Technology, 30 Aug.-2 Sept. 2005, pp:61-66
2. K. M Brown "System In Package "The Rebirth of SIP" Custom Integrated Circuits Conference, Proceedings of the IEEE 2004 3-6 Oct. 2004 pp:681-686
3. P. Garrou and R. Tummala, "Fundamentals of Wafer-Level Packaging," Fundamentals of Microsystems Packaging, Chapter 10, McGraw Hill Book Co., New York, N.Y., 2001.
4. M Topper and P Garrou "The Wafer-Level Packaging Evolution", Semiconductor International October 2004
5. Keith D Gann "Neo-Staking technology" issue of HDI Magazine, Dec. 1999
6. J-C Souriau et al "Wafer Level Processing Of 3D System In Package For RF And Data Applications" 55th Electronic Components and Technology Conf, Orlando, FL, May 2005, pp. 356-361.
7. J-C Souriau et a1 "Wafer Level Processing on Rebuilt Wafer for Chip Stacking" 7th Electronic Packaging Technology Conf, Singapore, Dec 2005, pp. 140-143.
8. E Fürgut "Taking Wafer Level Packaging to the Next Stage" Advanced Packaging Conference SEMICON Europa 2006, Munich, Germany