Wafer level embedding technology for 3D wafer level embedded package

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2009, Pages 1289-1296

  Kumar, Aditya ^a   Dingwei, Xia ^b   Sekhar, Vasarla Nagendra ^a   Lim, Sharon ^a   Keng, Chin ^a   Sharma, Gaurav ^a   Rao, Vempati Srinivas ^a   Kripesh, Vaidyanathan ^a   Lau, John H ^a,c   Kwong, Dim Lee ^a  

^a INSTITUTE OF MICROELECTRONICS   (Singapore)

^b Kinergy Pte Ltd   (Singapore)

^c HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

Author keywords

[No Author keywords available]

Indexed keywords

EMBEDDING PROCESS; EPOXY MOLDING COMPOUNDS; HIGHLY ACCELERATED STRESS TESTS; MOISTURE SENSITIVITY; MOLDING PROCESS; MOLDING TIME; PROCESS OPTIMIZATION; RELIABILITY TEST; SCANNING ACOUSTIC MICROSCOPY; THERMAL CYCLE; THREE-DIMENSIONAL (3D); VOID FORMATION; WAFER LEVEL; WAFER LEVEL PACKAGE; WARPAGES;

ACOUSTIC MICROSCOPES; DIES; ELECTROMAGNETIC COMPATIBILITY; OPTIMIZATION; PLASTIC MOLDS; PROCESS CONTROL; STEEL SHEET; THREE DIMENSIONAL;

COMPRESSION MOLDING;

EID: 70349659174     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2009.5074177     Document Type: Conference Paper

References (10)

1. J. C. Souriau, O. Lignier, M. Charrier, G Poupon, "Wafer Level Processing Of 3D System In Package For RF And Data Applications", in proc. IEEE Electron. Comp. Techno. Conf., US, 2005, pp. 356-361.
2. M. Brunnbauer, E. Furgut, G. Beer, T. Meyer, H. Hedler, J. Belonio, E. Nomura, K. Kiuchi, K. Kobayashi, "An Embedded Device Technology Based on a Molded Reconfigured Wafer" in Proc. IEEE Electron. Comp. Technol. Conf., US, 2006, pp. 547-551.
3. B. Keser, C. Amrine, T. Duong, Owen Fay, S. Hayes, G. Leal, W. Lytle, D. Mitchell, R. Wenzel "The Redistributed Chip Package: A Breakthrough for Advanced Packaging", in Proc. IEEE Electron. Comp. Technol. Conf., US, 2007, pp. 286-290.
4. R. Fillion, Charles Woychik, T. Zhang, D. Bitting, "Embedded Chip Build-Up Using Fine Line Interconnect", in Proc. IEEE Electron. Comp. Technol. Conf., US, 2007, pp. 49-53.
5. V. Kripesh, V. S. Rao, A. Kumar, G. Sharma, K. C. Houe, Z. Xiaowu, K. Y. Mong, N. Khan, and J. Lau, "Design and Develeopment of a Multi-Die Embedded Micro Wafer Level Package", in Proc. IEEE Electron. Comp. Technol. Conf., US, 2008, pp. 1544-1549.
6. T. Hamano, T. Kawahara, J-I Kasai, "Super CSPTM : WLCSP Solution for Memory and System LSI", in proc. of International Symposium on Advanced Packaging Materials, 1999, pp. 221-225.
7. A. Okuno, "Wafer Level CSP Process by VPES (Vacuum Printing Encapsulation Systems)", in proc. of International Symposium on Electron. Materials & Packaging, 2000, pp. 143-151.
8. T. Braun, K.-F. Becker, M. Koch, V. Bader, U. Oestermann, D. Manessis, R. Aschenbrenner, H. Reichl, "Wafer Level Encapsulation-A transfer Molding Approach to System in Package Generation", in proc. Electron. Package Technol. Conf., 2002, pp. 235-244.
9. A. Ostmann, A. Neumann, S. Weser, E. Jung, L. Bottcher and H. Reichl, "Realization of a Stackable Package Using Chip in Polymer Technology", in proc. IEEE Polytronic 2002 Conf., 2002, pp. 160-164.
10. C.-T. Ko, S. Chen, C.-W. Chiang, T.-Y. Kuo, Y.-C. Shih and Y.-H. Chen, "Embedded Active Device Packaging Technoloogy for Next-Generation Chip-in-Substrate Packages, CiSP", in proc. of ECTC 2006, US, pp. 322-329.