Performance simulation and architecture optimization for cmos image sensor pixels scaling down to 1.0 μm

IEEE Transactions on Electron Devices

Volumn 57, Issue 4, 2010, Pages 788-794

  Zhang, Fudi ^a   Zhang, Jianqi ^a   Yang, Cui ^a   Zhang, Xiang ^a  

^a XIDIAN UNIVERSITY   (China)

Author keywords

Cameras; Complementary metal oxide semiconductor (CMOS); Image sensors; Integrated optics; Modeling

Indexed keywords

ARCHITECTURE OPTIMIZATION; CMOS IMAGE SENSOR; COLOR FILTER ARRAYS; COMPLEMENTARY METAL OXIDE SEMICONDUCTORS; COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR (CMOS); DEVICE CHARACTERISTICS; DIELECTRIC STACK; DIFFRACTION EFFECTS; FINITE DIFFERENCE TIME DOMAINS; HEIGHT REDUCTION; MICRO-LENS; NEW APPROACHES; OPTICAL CHARACTERISTICS; OPTICAL EFFICIENCY; OPTICAL POWER; PERFORMANCE COMPARISON; PERFORMANCE SIMULATION; PHYSICAL LIMITATIONS; PIXEL ARCHITECTURES; PIXEL DIMENSION; SCALING DOWN; SIMULATION RESULT; VISIBLE LIGHT;

CAMERAS; CMOS INTEGRATED CIRCUITS; CROSSTALK; DIELECTRIC DEVICES; DIGITAL IMAGE STORAGE; FINITE DIFFERENCE TIME DOMAIN METHOD; IMAGE SENSORS; INTEGRATED OPTICS; LIGHT; OPTICAL MATERIALS; OPTIMIZATION; PHOTONICS;

PIXELS;

EID: 77950300378     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2010.2041858     Document Type: Article

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