Evaluation of threshold-voltage variation in silicon on thin buried oxide complementary metal-oxide-semiconductor and its impact on decreasing standby leakage current

Japanese Journal of Applied Physics

Volumn 48, Issue 4 PART 2, 2009, Pages

  Sugii, Nobuyuki ^a   Tsuchiya, Ryuta ^a   Ishigaki, Takashi ^a   Morita, Yusuke ^a   Yoshimoto, Hiroyuki ^a   Iwamatsu, Toshiaki ^b   Oda, Hidekazu ^b   Inoue, Yasuo ^b   Hiramoto, Toshiro ^c   Kimura, Shin'ichiro ^a  

^a HITACHI LTD   (Japan)

^b RENESAS TECHNOLOGY CORP   (Japan)

^c INSTITUTE OF INDUSTRIAL SCIENCE   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BURIED OXIDES; COMPLEMENTARY METAL OXIDE SEMICONDUCTORS; FULLY SILICIDED METAL GATE; GATE LENGTH; HALO IMPLANTATION; IMPURITY CONCENTRATION; METAL-GATE; OFF-STATE LEAKAGE CURRENT; SHORT-CHANNEL EFFECT; SILICON-ON-INSULATORS; STAND-BY LEAKAGE; STANDARD DEVIATION; VOLTAGE VARIATION;

DIELECTRIC DEVICES; LEAKAGE CURRENTS; METALS; SILICIDES; THRESHOLD VOLTAGE; TRANSISTORS;

SEMICONDUCTING SILICON;

EID: 77950295923     PISSN: 00214922     EISSN: 13474065     Source Type: Journal    
DOI: 10.1143/JJAP.48.04C043     Document Type: Article

References (13)

1. T. C. Chen: IEEE Int. Solid-State Circuits Conf., 2006, p. 1.
2. A. Asenov: VLSI Tech. Dig., 2007, p. 86.
3. R. Tsuchiya, M. Horiuchi, S. Kimura, M. Yamaoka, T. Kawahara, S. Maegawa, T. Ipposhi, Y. Ohji, and H. Matsuoka: IEDM Tech. Dig., 2004, p. 631.
4. T. Ishigaki, R. Tsuchiya, Y. Morita, N. Sugii, S. Kimura, T. Iwamatsu, T. Ipposhi, Y. Inoue, and T. Hiramoto: Jpn. J. Appl. Phys. 47 (2008) 2585.
5. Y. Morita, R. Tsuchiya, T. Ishigaki, N. Sugii, T. Iwamatsu, T. Ipposhi, H. Oda, Y. Inoue, K. Torii, and S. Kimura: VLSI Tech. Dig., 2008, p. 166.
6. K. Takeuchi, T. Fukai, T. Tsunomura, A. T. Putra, A. Nishida, S. Kamohara, and T. Hiramoto: IEDM Tech. Dig., 2007, p. 467.
7. T. Tsunomura, A. Nishida, F. Yano, A. T. Putra, K. Takeuchi, S. Inaba, S. Kamohara, K. Terada, T. Hiramoto, and T. Mogami: VLSI Tech. Dig., 2008, p. 156.
8. N. Sugii, R. Tsuchiya, T. Ishigaki, Y. Morita, H. Yoshimoto, K. Torii, and S. Kimura: IEDM Tech. Dig., 2008, p. 249.
9. R. B. D'Agostino: Goodness-of-Fit Techniques (Marcel Dekker, New York, 1986) p. 367.
10. M. J. M. Pelgrom, AAD C. J. Duinmaijer, and A. P. G. Welbers: IEEE J. Solid-State Circuits 24 (1989) 1433.
11. A. Asenov and S. Saini: IEEE Trans. Electron Devices 47 (2000) 805.
12. T. Tanaka, T. Usuki, Y. Momiyama, and T. Sugii: VLSI Tech. Dig., 2000, p. 136.
13. T. Ohtou, N. Sugii, and T. Hiramoto: IEEE Electron Device Lett. 28 (2007) 740.