Wide-range threshold voltage controllable silicon on thin buried oxide integrated with bulk complementary metal oxide semiconductor featuring fully silicided NiSi gate electrode

Japanese Journal of Applied Physics

Volumn 47, Issue 4 PART 2, 2008, Pages 2585-2588

  Ishigaki, Takashi ^a   Tsuchiya, Ryuta ^a   Morita, Yusuke ^a   Sugii, Nobuyuki ^a   Kimura, Shinichiro ^a   Iwamatsu, Toshiaki ^b   Ipposhi, Takashi ^b   Inoue, Yasuo ^b   Hiramoto, Toshiro ^c  

^a HITACHI LTD   (Japan)

^b RENESAS TECHNOLOGY CORP   (Japan)

^c INSTITUTE OF INDUSTRIAL SCIENCE   (Japan)

Author keywords

Back gate; Fluctuation; Fully depleted silicon on insulator (FD SOI); Fully silicided (FUSI); Hybrid; Metal gate; Raised source drain; Si selective epitaxial growth; Thin buried oxide (BOX); Variability; Variation

Indexed keywords

CHARGE COUPLED DEVICES; ELECTRIC CONDUCTIVITY; EPITAXIAL GROWTH; FIELD EFFECT TRANSISTORS; FINITE DIFFERENCE METHOD; LOGIC CIRCUITS; METALLIC COMPOUNDS; MOLECULAR BEAM EPITAXY; MOS DEVICES; MOSFET DEVICES; SEMICONDUCTING SILICON; SEMICONDUCTOR GROWTH; SEMICONDUCTOR MATERIALS; SILICIDES; SILICON; SILICON ON INSULATOR TECHNOLOGY; THRESHOLD VOLTAGE; TRANSISTORS;

BACK-GATE; FLUCTUATION; FULLY DEPLETED SILICON ON INSULATOR (FD SOI); FULLY SILICIDED (FUSI); HYBRID; METAL GATE; RAISED SOURCE/DRAIN; SI SELECTIVE EPITAXIAL GROWTH; THIN BURIED OXIDE (BOX); VARIABILITY; VARIATION;

SEMICONDUCTING SILICON COMPOUNDS;

EID: 54249161933     PISSN: 00214922     EISSN: 13474065     Source Type: Journal    
DOI: 10.1143/JJAP.47.2585     Document Type: Article

References (8)

1. T. Mizuno, J. Okamura, and A. Toriumi: IEEE Trans. Electron Devices 41 (1994) 2216.
2. A. Asenov, S. Kaya, and A. R. Brown: IEEE Trans. Electron Devices 50 (2003) 1254.
3. R. Tsuchiya, M. Horiuchi, S. Kimura, M. Yamaoka, T. Kawahara. S. Maegawa, T. Ipposhi, Y. Ohji, and H. Matsuoka: IEDM Tech. Dig., 2004, p. 631.
4. M. Fujiwara, T. Morooka, N. Yasutake, K. Ohuchi, N. Aoki, H. Tanimoto, M. Kondo, K. Miyano, S. Inaba, K. Ishimaru, and H. Ishiuchi: IEEE Int. SOI Conf., 2005, p. 180.
5. C. Gallon, C. Fenouillet-Beranger, A. Vandooren, F. Boeuf, S. Monfray, F. Payer, S. Orain, V. Fiori, F. Salvetti, N. Loubet, C. Charbuillet, A. Toffoli, F. Allain, K. Romanjek, I. Cayrefourcq, B. Ghyselen, C. Mazure, D. Deille, F. Judong, C. Perrot, M. Hopstaken, P. Scheblin, P. Rivallin, L. Brevard, O. Faynot, S. Cristoloveanu, and T. Skotnicki: IEEE Int. SOI Conf., 2006, p. 17.
6. H. Y. Chen, C. Y. Chang, C. C. Huang, T. X. Chung, S. D. Liu, J. R. Hwang, Y. H. Liu, Y. J. Chou, H. J. Wu, K. C. Shu, C. K. Huang, J. W. You, J. J. Shin, C. K. Chen, C. H. Lin, J. W. Hsu, B. C. Perng, P. Y. Tsai, C. C. Chen, J. H. Shieh, H. J. Tao, S. C. Chen, T. S. Gau, and F. L. Yang: Symp. VLSI Technology, 2005, p. 16.
7. T. Ohtou, N. Sugii, and T. Hiramoto: IEEE Electron Device Lett. 28 (2007) 740.
8. M. Yang, M. leong, L. Shi, K. Chan, V. Chan, A. Chou, E. Gusev, K. Jenkins, D. Boyd, Y. Ninomiya, D. Pendleton, Y. Surpris, D. Heenan, J. Ott, K. Guarini, C. D'Emic, M. Cobb, P. Mooney, B. To, N. Rovedo, J. Benedict, R. Mo, and H. Ng: IEDM Tech. Dig., 2003, p. 18.7.1.