Atomistic modeling of realistically extended semiconductor devices with NEMO and OMEN

Computing in Science and Engineering

Volumn 12, Issue 2, 2010, Pages 28-35

  Klimeck, Gerhard ^a   Luisier, Mathieu ^a  

^a PURDUE UNIVERSITY   (United States)

Author keywords

Atomistic modeling and simulation; Computer aided design; High performance computing; Nanoelectronics; Nanoscale semiconductor devices; Nanotechnology; Parallel computing

Indexed keywords

ATOMISTIC MODELING; EXPERIMENTAL DATA; GUIDING EXPERIMENT; HIGH-PERFORMANCE COMPUTING; KEY ELEMENTS; NANOSCALE SEMICONDUCTOR DEVICES; PARALLEL COMPUTING; QUANTUM MECHANICAL EFFECTS; SIMULATION ENGINE; TOOLSETS;

COMPUTER AIDED DESIGN; COMPUTER SIMULATION; NANOELECTRONICS; NANOSTRUCTURED MATERIALS; PARALLEL ARCHITECTURES; QUANTUM THEORY; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR SWITCHES;

SEMICONDUCTOR DEVICE MODELS;

EID: 77949987659     PISSN: 15219615     EISSN: None     Source Type: Journal    
DOI: 10.1109/MCSE.2010.32     Document Type: Article

References (21)

1. R.C. Bowen et al., "Quantitative Resonant Tunneling Diode Simulation," J. Applied Physics, vol.81, no.7, 1997, pp. 3207-3213, doi:10.1063/1.364151.
2. P. Van der Wagt and G. Klimeck, Method and System for Generating a Memory Cell, US Patent 6,667,490 to Raytheon TI Systems, Patent and Trademark Office, 2003.
3. G. Klimeck et al., "sp3s* Tight-Binding Parameters for Transport Simulations in Compound Semiconductors," Superlattices and Microstructures, vol.27, 2000, pp. 519-524, doi:10.1006/spmi.2000.0862.
4. G. Klimeck et al., "Development of a Nanoelectronic 3-D (NEMO-3-D) Simulator for Multimillion Atom Simulations and Its Application to Alloyed Quantum Dots," Computer Modeling in Eng. and Science (CMES), vol.3, no.5, 2002, pp. 601-642.
5. T.B. Boykin et al., "Diagonal Parameter Shifts Due to Nearest-Neighbor Displacements in Empirical Tight- Binding Theory," Physics Rev. B, vol. 66, no. 12, 2002; doi:10.1103/PhysRevB.66.125207.
6. G. Klimeck et al., "Atomistic 6. Simulation of Realistically Sized Nanodevices Using NEMO-3-D: Part I- Models and Benchmarks," IEEE Trans. Electron Devices, vol. 54, no. 9, 2007, pp. 2079-2089, doi:10.1109/ TED.2007.902879.
7. M. Luisier et al., "Atomistic Simulation of Nanowires in the sp3d5s* Tight-Binding Formalism: From Boundary Conditions to Strain Calculations," Physics Rev. B, vol.74, no.20, 2006, doi:10.1103/ PhysRevB.74.205323.
8. M. Luisier and G. Klimeck, "Atomistic Full-Band Simulations of Silicon Nanowire Transistors: Effects of Electron-Phonon Scattering," Physics Rev. B, vol.94, no.22, 2009; doi:10.1063/1.3140505.
9. R.K. Lake et al., "Interface Roughness and Polar Optical Phonon Scattering and the Valley Current in Resonant Tunneling Devices," Superlattices and Microstructures, vol.20, 1996, pp. A163-A164, doi:10.1088/0268-1242/13/8A/046p.279.
10. G. Klimeck, "Parallelization of the Nanoelectronic Modeling Tool (NEMO-1-D) on a Beowulf Cluster," J. Computational Electronics, vol.1, nos. 1-2, 2002, pp. 75-79, doi:10.1023/A:1020767811814.
11. B.P. Haley et al., "Advancing Nanoelectronic Device Modeling through Peta-Scale Computing and Deployment on nanoHUB," J. Physics Conf. Series, vol.180, no.1, 2009, doi:10.1088/1742-6596/180/1/012075.
12. M. Luisier et al., "Full-Band and Atomistic Simulation of Realistic 40 nm InAs HEMT," Proc. IEEE Int'l Electronic Devices Meeting, IEEE Press, 2008, pp. 1-4, doi:10.1109/IEDM.2008.4796842.
13. N. Kharche et al., "Valley-Splitting in Strained Silicon Quantum Wells Modeled with 2 Degree Miscuts, Step Disorder, and Alloy Disorder," Applied Physics Letters, vol.84, no 9, 2004, pp. 115-117, doi:10.1063/1.2591432.
14. G.P. Lansbergen et al., "Gate Induced Quantum Confinement Transition of a Single Dopant Atom in a Si FinFET," Nature Physics, vol.4, 2008, pp. 656-661, doi:10.138/nphys994.
15. M. Usman et al., "Moving Towards Nano-TCAD Through Multi-Million Atom Quantum Dot Simulations Matching Experimental Data," IEEE Trans. Nanotechnology, vol.8, no.3, 2009, pp. 330-344, doi:10.1109/TNANO.2008.2011900.
16. J. Tatebayashi, M. Nishioka, and Y. Arakawa, "Over 1.5 μm Light Emission from InAs Quantum Dots Embedded in InGaAs Strain-Reducing Layer Grown by Metalorganic Chemical Vapor Deposition," Applied Physics Letters, vol.78, no.22, 2001, p. 3469, doi:10.1063/1.1375842. (Pubitemid 33666795)
17. D. Kim and J. del Alamo, "30 nm E-mode InAs PHEMTs for THz and Future Logic Applications," IEEE Int'l Electronic Device Meeting, IEEE Press, 2008, pp. 719-722.
18. M. Luisier, A. Schenk, and W. Fichtner, "Atomistic Treatment of Interface Roughness in Si Nanowire Transistors with Different Channel Orientations," Applied Physics Letters, vol.90, no.10, 2007, doi:10.1063/1.2711275. (Pubitemid 46398423)
19. M. Luisier and G. Klimeck, "Full-Band and Atomistic Simulation of N- and P-Doped Double-Gate Mosfets for the 22 nm Technology Node," Proc. Int'l Conf. Simulation Semiconductor Processes and Devices (SISPAD), IEEE Press, 2008, pp. 1-4, doi:10.1109/ SISPAD.2008.4648226.
20. M. Luisier and G. Klimeck, "Atomistic, Full-Band Design Study of InAs Band-to-Band Tunneling Field- Effect Transistors," IEEE Electron Device Letters, vol.30, 2009, pp. 602-604, doi:10.1109/LED.2009.2020442.
21. M. Luisier and G. Klimeck, "Performance Analysis of Statistical Samples of Graphene Nanoribbon Tunneling Transistors with Line Edge Roughness," Applied Physics Letters, vol.94, no.22, 2009; doi:10.1063/1.3140505.