Identifying the bottlenecks to the RF performance of FinFETs

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 2010, Pages 111-116

  Subramanian, V ^a   Mercha, A ^b   Parvias, B ^b   Dehan, M ^b   Groeseneken, G ^b   Sansen, W ^c   Decoutere, S ^b  

^a IBM INDIA RESEARCH LAB   (India)

^b IMEC   (Belgium)

^c UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

FIGURES OF MERITS; FINFETS; HIGH FREQUENCY; PARASITIC CAPACITANCE; PARASITIC ELEMENT; PARASITIC SERIES RESISTANCE; PARASITICS; RF PERFORMANCE; SCALING RELATIONS;

CAPACITANCE; DESIGN;

EMBEDDED SYSTEMS;

EID: 77949984633     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSI.Design.2010.19     Document Type: Conference Paper

References (11)

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2. G. Vellianitis, M. van Dal, L. Witters, et al, "Gatestacks for high performance FinFETs", IEDM Tech. Dig., pp.681-684, 2007.
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9. G. Chen, R. Huang, X. Zhang, L. Yang, et. al, "Spacer design between source/drain and gate for high performance FinFETs", Proc. Intl. Conf. Solid State and IC technology, vol. 1, pp. 122-125, 2004.
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