Finite element simulations of parasitic capacitances related to multiple-gate field-effect transistors architectures

2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systms - Digest of Papers, SiRF

Volumn , Issue , 2008, Pages 183-186

  Moldovan, O ^a   Lederer, D ^b   Iniguez B ^a   Raskin, J P ^c  

^a UNIVERSITAT ROVIRA I VIRGILI   (Spain)

^b UNIVERSITY COLLEGE CORK   (Ireland)

^c UNIVERSITÉ CATHOLIQUE DE LOUVAIN   (Belgium)

Author keywords

Cutoff frequency; FinFET; Finite element simulations; Fringing capacitance; MuGFET

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; ELECTRONICS INDUSTRY; EPITAXIAL GROWTH; FIELD EFFECT TRANSISTORS; FINITE ELEMENT METHOD; FINS (HEAT EXCHANGE); HETEROJUNCTION BIPOLAR TRANSISTORS; INTEGRATED CIRCUITS; MOLECULAR BEAM EPITAXY; MOSFET DEVICES; NONMETALS; RADIOFREQUENCY SPECTROSCOPY; SEMICONDUCTING SILICON COMPOUNDS; SILICON; TRANSISTORS;

CUT-OFF FREQUENCIES; CUTOFF FREQUENCY; DIE AREA; DOUBLE GATES; FIN SPACING; FINFET; FINFETS; FINITE ELEMENT SIMULATIONS; FRINGING CAPACITANCE; GEOMETRICAL PARAMETERS; MOSFETS; MUGFET; MULTIPLE-GATE; PARASITIC CAPACITANCES; PARASITIC SOURCE; RF SYSTEMS; SELECTIVE EPITAXIAL GROWTH; SINGLE GATE; SOURCE AND DRAIN; TECHNOLOGICAL SOLUTIONS; TRIPLE-GATE;

MONOLITHIC INTEGRATED CIRCUITS;

EID: 52049124284     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SMIC.2008.52     Document Type: Conference Paper

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