FloRA: Coarse-grained reconfigurable architecture with floating-point operation capability

Proceedings of the 2009 International Conference on Field-Programmable Technology, FPT'09

Volumn , Issue , 2009, Pages 376-379

  Lee, Dongwook ^a   Jo, Manhwee ^a   Han, Kyuseung ^a   Choi, Kiyoung ^a  

^a Seoul National University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP IMPLEMENTATION; COARSE GRAINED RECONFIGURABLE ARCHITECTURE; FLOATING POINT OPERATIONS; FLOATING-POINT FUNCTIONS; INTEGER FUNCTIONS; JPEG DECODERS; PHYSICS ENGINE; PROCESSING ELEMENTS; RUNNING APPLICATIONS; RUNTIMES; TWO-DIMENSIONAL ARRAYS;

DIGITAL ARITHMETIC; EMBEDDED SYSTEMS;

COMPUTER ARCHITECTURE;

EID: 77949421428     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPT.2009.5377609     Document Type: Conference Paper

References (10)

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