Construction of polyvalent error control codes for multilevel memories

Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Volumn 2, Issue , 2000, Pages 751-754

  Gregori, Stefano ^a   Ferrari, Pietro ^a   Micheloni, Rino ^b   Torelli, Guido ^a  

^a UNIVERSITY OF PAVIA   (Italy)

^b STMICROELECTRONICS   (Italy)

Author keywords

Error control codes; Multilevel memories

Indexed keywords

DATA PROTECTION; ENCODING/DECODING CIRCUITS; ERROR CONTROL; ERROR CONTROL CODE; IMPLEMENTATION ASPECTS; MEMORY CELL; MULTILEVEL MEMORY; MULTILEVEL STORAGE; SEMICONDUCTOR MEMORY TECHNOLOGY; VARIABLE NUMBER;

SEMICONDUCTOR STORAGE;

EID: 0004078651     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICECS.2000.912986     Document Type: Conference Paper

References (10)

1. B. Riccò, et al, "Nonvolatile multilevel memories for digital applications", Proceedings of the IEEE, vol.86, no.12, Dec. 1998, pp. 2399-2421.
2. G. Birk, D. G. Elliott, B. F. Cockburn, "A comparative simulation study of four multilevel DRAMs", Records of the 1999 IEEE International Workshop on Memory Technology, Design and Testing (MTDT), 1999, pp. 102-109.
3. M. Bauer, et al, "A multilevel-cell 32 Mb Flash memory", 1995 IEEE ISSCC Dig. Tech. Pap., pp. 132-133.
4. T. Okuda, T. Murotani, "A four-level storage 4-Gb DRAM", IEEE J. Solid-Slate Circuits, vol.32, no.11, Nov. 1997, pp. 1743-1747.
5. G. Torelli, A. Manstretta, R. Gastaldi, P. Rolandi, "Mixed serial-parallel sensing scheme for a 64-Mbit 4-bit/Cell factory programmed OTP-ROM", Microelectronics Journal, no.30, 1999, pp. 875-886.
6. M. Horiguchi, M. Aoki, Y. Nakagome, S. Ikenaga, K. Shimohigashi, "An experimental large-capacity semiconductor file memory using 16-levels/cell storage", IEEE J. Solid-State Circuits, vol.23, no.1, Feb. 1988, pp. 27-33.
7. C. V. Srinivasan, "Codes for error correction in high-speed memory systems - part 1: correction of cell defects in integrated memories", IEEE Trans. Comput., vol.C-20, no.8, Aug. 1971, pp. 882-888.
8. R. M. Goodman, M. Sayano, "The reliability of semiconductor RAM memories with on-chip error-correction coding", IEEE Trans. Inform. Theory, vol.37, no.3, May 1991, pp. 884-896.
9. C. L. Chen, M. Y. Hsiao, "Error-correcting codes for semiconductor memory applications: a state-of-the-art review", IBM J. Res. Develop., vol.28, no.2, Mar. 1984, pp. 124-134.
10. R. E. Blahut, Theory and Practice of Error Control Codes, Addison-Wesley, 1983.