메뉴 건너뛰기




Volumn 12, Issue 10, 2004, Pages 1015-1027

Power estimation techniques for FPGAs

Author keywords

Capacitance; Estimation; Field programmable gate arrays (FPGAs); Modeling; Power; Switching activity

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CAPACITANCE; CMOS INTEGRATED CIRCUITS; LARGE SCALE SYSTEMS; SWITCHING;

EID: 6344238665     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2004.831478     Document Type: Conference Paper
Times cited : (99)

References (27)
  • 5
    • 0028711580 scopus 로고
    • A survey of power estimation techniques in VLSI circuits
    • Dec.
    • F. Najm, "A survey of power estimation techniques in VLSI circuits," IEEE Trans. VLSI Syst., vol. 2, pp. 446-455, Dec. 1994.
    • (1994) IEEE Trans. VLSI Syst. , vol.2 , pp. 446-455
    • Najm, F.1
  • 6
    • 0346479458 scopus 로고    scopus 로고
    • Estimating circuit activity in combinational CMOS digital circuits
    • Apr.-June
    • H. Soeleman, K. Roy, and T.-L. Chou, "Estimating circuit activity in combinational CMOS digital circuits," IEEE Des. Test Comput., pp. 112-119, Apr.-June 2000.
    • (2000) IEEE Des. Test Comput. , pp. 112-119
    • Soeleman, H.1    Roy, K.2    Chou, T.-L.3
  • 7
    • 0027003872 scopus 로고
    • On average power dissipation and random pattern testability of CMOS combinational logic networks
    • A. Shen, A. Ghosh, S. Devadas, and K. Keutzer, "On average power dissipation and random pattern testability of CMOS combinational logic networks," in Proc. IEEE Int. Conf. Computer-Aided Design, 1992, pp. 402-407.
    • (1992) Proc. IEEE Int. Conf. Computer-aided Design , pp. 402-407
    • Shen, A.1    Ghosh, A.2    Devadas, S.3    Keutzer, K.4
  • 8
    • 84964426030 scopus 로고    scopus 로고
    • LUT-based FPGA technology mapping for power minimization with optimal depth
    • H. Li, W.-K. Mak, and S. Katkoori, "LUT-based FPGA technology mapping for power minimization with optimal depth," in Proc. IEEE Computer Society Workshop VLSI, 2001, pp. 123-128.
    • (2001) Proc. IEEE Computer Society Workshop VLSI , pp. 123-128
    • Li, H.1    Mak, W.-K.2    Katkoori, S.3
  • 12
    • 2442513166 scopus 로고    scopus 로고
    • Interconnect capacitance estimation for FPGAs
    • Yokohama, Japan
    • _, "Interconnect capacitance estimation for FPGAs," in Proc. IEEE Asia South Pacific Design Automation Conf., Yokohama, Japan, 2004, pp. 713-718.
    • (2004) Proc. IEEE Asia South Pacific Design Automation Conf. , pp. 713-718
  • 15
    • 0028259317 scopus 로고
    • Flowmap: An optimal technology mapping algorithm for delay optimization in look-up-table based FPGA designs
    • Jan.
    • J. Cong and Y. Ding, "Flowmap: an optimal technology mapping algorithm for delay optimization in look-up-table based FPGA designs," IEEE Trans. Computer-Aided Design, vol. 13, pp. 1-12, Jan. 1994.
    • (1994) IEEE Trans. Computer-aided Design , vol.13 , pp. 1-12
    • Cong, J.1    Ding, Y.2
  • 17
    • 0027544156 scopus 로고
    • Transition density: A new measure of activity in digital circuits
    • Feb.
    • F. Najm, "Transition density: a new measure of activity in digital circuits," IEEE Trans. Computer-Aided Design, vol. 12, pp. 310-323, Feb. 1993.
    • (1993) IEEE Trans. Computer-aided Design , vol.12 , pp. 310-323
    • Najm, F.1
  • 19
    • 0032627268 scopus 로고    scopus 로고
    • Power-dissipation driven FPGA place and route under timing constraints
    • May
    • K. Roy, "Power-dissipation driven FPGA place and route under timing constraints," IEEE Trans. Circuits Syst., vol. 46, pp. 634-637, May 1999.
    • (1999) IEEE Trans. Circuits Syst. , vol.46 , pp. 634-637
    • Roy, K.1
  • 20
    • 2442465683 scopus 로고    scopus 로고
    • Power and delay reduction via simultaneous logic and placement optimization in FPGAs
    • B. Kumthekar and F. Somenzi, "Power and delay reduction via simultaneous logic and placement optimization in FPGAs," in Proc. IEEE Design, Automation Test Eur. Conf., 2000, pp. 202-207.
    • (2000) Proc. IEEE Design, Automation Test Eur. Conf. , pp. 202-207
    • Kumthekar, B.1    Somenzi, F.2
  • 22
    • 0029542569 scopus 로고
    • An empirical model for accurate estimation of routing delay in EPGAs
    • T. Karnik and S.-M. Kang, "An empirical model for accurate estimation of routing delay in EPGAs," in Proc. IEEE Int. Conf. Computer-Aided Design, 1995, pp. 328-331.
    • (1995) Proc. IEEE Int. Conf. Computer-aided Design , pp. 328-331
    • Karnik, T.1    Kang, S.-M.2
  • 23
    • 0042635650 scopus 로고    scopus 로고
    • Fast timing-driven partitioning-based placement for island style FPGAs
    • P. Maidee, C. Ababei, and K. Bazargan, "Fast timing-driven partitioning-based placement for island style FPGAs," in Proc. IEEE Design Automation Conf., 2003, pp. 598-603.
    • (2003) Proc. IEEE Design Automation Conf. , pp. 598-603
    • Maidee, P.1    Ababei, C.2    Bazargan, K.3
  • 24
    • 0037316907 scopus 로고    scopus 로고
    • Adaptive delay estimation for partitioning-driven PLD placement
    • Feb.
    • M. Hutton, K. Adibsamii, and A. Leaver, "Adaptive delay estimation for partitioning-driven PLD placement," IEEE Trans. VLSI Syst., vol. 11, pp. 60-63, Feb. 2003.
    • (2003) IEEE Trans. VLSI Syst. , vol.11 , pp. 60-63
    • Hutton, M.1    Adibsamii, K.2    Leaver, A.3
  • 26
    • 2442601233 scopus 로고    scopus 로고
    • [Online]
    • (2003) Xilinx Power Tools. [Online], Available: http://www.xilinx.com/ ise/power_tools
    • (2003) Xilinx Power Tools


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.