Compact capacitance modeling of a 3-terminal FET at zero drain-source voltage

Solid-State Electronics

Volumn 54, Issue 5, 2010, Pages 520-523

  Iñiguez, Benjamin ^a   Moldovan, Oana ^b  

^a UNIVERSITAT ROVIRA I VIRGILI   (Spain)

^b UNIVERSITAT AUTÒNOMA DE BARCELONA   (Spain)

Author keywords

Compact device modeling; Double Gate MOSFETs; Multi Gate MOSFETs

Indexed keywords

ANALYTIC EXPRESSIONS; BENCHMARK TESTS; C-V CHARACTERISTIC; CAPACITANCE MODEL; CAPACITANCE MODELING; CHARGE CONTROL MODEL; COMPACT DEVICE MODELING; COMPACT MODEL; COMPACT MODELING; DOUBLE-GATE; DOUBLE-GATE MOSFETS; DRAIN CHARGE; DRAIN VOLTAGE; DRAIN-SOURCE VOLTAGE; MOSFETS; SHEET DENSITY; SURROUNDING-GATE; TERMINAL DEVICES;

CAPACITANCE; FIELD EFFECT TRANSISTORS; MESFET DEVICES; MOSFET DEVICES;

POWDERS;

EID: 77949278380     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2009.12.039     Document Type: Article

References (7)

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