Novel 3-D coaxial interconnect system for use in system-in-package applications

IEEE Transactions on Advanced Packaging

Volumn 33, Issue 1, 2010, Pages 37-47

  LaMeres, Brock J ^a   McIntosh, Christopher ^a   Abusultan, Monther ^a  

^a Idaho National Laboratory   (United States)

Author keywords

Integrated circuit (IC) packaging; Simultaneous switching noise (SSN); System in package (SiP); Three dimensional (3 D) chip stacking

Indexed keywords

CHIP STACKING; COAXIAL TRANSMISSION LINES; COPLANAR TRANSMISSION LINES; DESIGN PROCESS; ELECTRICAL PERFORMANCE; ETCHING PROCESS; FABRICATION SEQUENCE; FINITE ELEMENT ANALYSIS; GROUND CONTACTS; HIGH-SPEED; IMPEDANCE DISCONTINUITIES; INTEGRATED CIRCUIT PACKAGING; INTERCONNECT SYSTEMS; LOW IMPEDANCE; MECHANICAL STRAIN; NEW APPROACHES; OFF-CHIP; ON CHIPS; SELF ALIGNMENT; SIGNAL PATHS; SILICON SUBSTRATES; SIMULTANEOUS SWITCHING NOISE; SWITCHING SIGNALS; SYSTEM-IN-PACKAGE; SYSTEM-IN-PACKAGE APPLICATIONS; WIRE BONDS;

CABLES; COAXIAL CABLES; DIES; ELECTRIC LINES; FINITE ELEMENT METHOD; INTEGRATED CIRCUITS; INTERCONNECTION NETWORKS; INTERNET PROTOCOLS; JITTER; PACKAGING; SANITARY SEWERS; SWITCHING; TELECOMMUNICATION CABLES; THREE DIMENSIONAL; TRANSMISSION LINE THEORY;

CHIP SCALE PACKAGES;

EID: 77949271501     PISSN: 15213323     EISSN: None     Source Type: Journal    
DOI: 10.1109/TADVP.2009.2033942     Document Type: Article

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