New 3-D chip stacking architectures by wire-on-bump and bump-on-flex

IEEE Transactions on Advanced Packaging

Volumn 31, Issue 2, 2008, Pages 367-376

  Lee, Baik Woo ^a   Tsai, Jui Yun ^a   Jin, Hotae ^b   Yoon, Chong K ^a   Tummala, Rao R ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b Samsung Electronics Corporation Baebang Myeon   (South Korea)

Author keywords

3 D module; Bump on flex (BOF); Reliability; Three dimensional (3 D) chip stacking; Vertical interconnections; Wire on bump (WOB)

Indexed keywords

FINITE ELEMENT METHOD; MICROPROCESSOR CHIPS; SEMICONDUCTING SILICON; SURFACE MOUNT TECHNOLOGY; THERMAL CYCLING;

BUMP-ON-FLEX TECHNOLOGY; CHIP STACKING; WIRE-ON-BUMP TECHNOLOGY;

CHIP SCALE PACKAGES;

EID: 44449086461     PISSN: 15213323     EISSN: None     Source Type: Journal    
DOI: 10.1109/TADVP.2007.909454     Document Type: Article

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