40-Gb/s package design using wire-bonded plastic ball grid array

IEEE Transactions on Advanced Packaging

Volumn 31, Issue 2, 2008, Pages 258-266

  Kam, Dong Gun ^a   Kim, Joungho ^b  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

Author keywords

Ball grid array (BGA); Discontinuity cancellation; High speed serial link; Package electrical design; Power distribution network (PDN); Return current path

Indexed keywords

BALL GRID ARRAYS; COMPUTER SIMULATION; ELECTRIC POWER DISTRIBUTION; JITTER; OPTIMIZATION; REFLECTOMETERS; TIME DOMAIN ANALYSIS;

BONDING WIRES; PACKAGE ELECTRICAL DESIGN; TIME DOMAIN REFLECTOMETRY (TDR); WIRE-BONDED PLASTIC BALL GRID ARRAY (WB-PBGA) TECHNOLOGY;

ELECTRONICS PACKAGING;

EID: 44449092639     PISSN: 15213323     EISSN: None     Source Type: Journal    
DOI: 10.1109/TADVP.2008.923381     Document Type: Article

References (19)

1. W. Dally and J. Poulton, Digital Systems Engineering. New York: Cambridge Univ. Press, 1998, pp. 1-24.
2. D. Burger, J. R. Goodman, and A. Kagi, "Memory bandwidth limitations of future microprocessors," in Proc. 23rd Annu. Int. Symp. Comput. Archit., 1996, pp. 78-89.
3. H. Hofstee, "Future microprocessors and off-chip SOP interconnect," IEEE Trans. Adv. Packag., vol. 27, no. 2, pp. 301-303, May 2004.
4. C. Yang and M. Horowitz, "A 0.8-μ CMOs 2.5 Gb/s oversampling receiver and transmitter for serial links," IEEE J. Solid-State Circuits, vol. 31, no. 12, pp. 2015-2023, Dec. 1996.
5. S. Galal and B. Razavi, "40-Gb/s amplifier and ESD protection circuit in 0.18-μ CMOS technology," IEEE J. Solid-State Circuits, vol. 39, pp. 2389-2396, Dec. 2004.
6. J. Kim, J.-K. Kim, B.-J. Lee, M.-S. Hwang, H.-R. Lee, S.-H. Lee, N. Kim, D.-K. Jeong, and W. Kim, "Circuit techniques for a 40 Gb/s transmitter in 0.13-μm CMOS," in Proc. IEEE Int. Solid-State Circuits Conf., 2005, pp. 150-151.
7. L. Shan, M. Meghelli, J.-H. Kim, J. M. Trewhella, and M. M. Oprysko, "Simulation and design methodology for a 50-gb/s multiplexer/de multiplexer package," IEEE Trans. Adv. Packag., vol. 25, no. 2, pp. 248-254, May 2002.
8. X. Zhou and N. J. Fang, "Performance of low cost PBGA package for 10 Gb/s applications," Proc. Electr. Performance Electron. Packag., pp. 71-94, 2002.
9. R. Emigh, "Electrical design for high data rate signals in conventional, BT based PBGA substrates using wire bonded interconnection," in Proc. 5th Electron. Packag. Technol. Conf (EPTC 2003), Singapore, 2003, pp. 517-522.
10. M. Megahed, P. Zilaro, and M. Khaw, "Design and analysis of low cost IC package solution for 10-gbit/s applications," in IEEE MTT-S Int. Microw. Symp. Dig., 2001, pp. 1899-1902.
11. D. E. Riemer, "Packaging design of wide-angle phased-array antenna for frequencies above 20 GHz," IEEE Trans. Antennas Propagat., vol. 43, no. 9, pp. 915-920, Sep. 1995.
12. S. A. Chickamenahalli, H. Braunisch, S. Srinivasan, J. He, U. Shrivastava, and B. Sankman, "RF packaging and passives: Design, fabrication, measuremeent, and validation of package embedded inductors," IEEE Trans. Adv. Packag., Vol. 28, no. 4, pp. 665-673, Nov. 2005.
13. J. Lee, S. Pinel, J. Papapolymerou, J. Laskar, and M. M. Tentzeris, "Low-loss LTCC cavity filters using system-on-package technology at 60 GHz," IEEE Trans. Microw. Theory Tech., vol. 53, no. 12 pp. 3817-3824, Dec. 2005.
14. P. C. Cherry and M. F. Iskander, "FDTD analysis of high frequency electronic interconnection effects," IEEE Trans. Microw. Theory Tech., Vol. 43, no. 10, pp. 2445-2451, Oct. 1995.
15. H. Johnson and M. Graham, High Speed Signal Propagation: Advanced Black Magic. Englewood Cliffs, NJ: Prentice- Hall, 2003.
16. S. Ahn, J. Park, D. Chung, and J. Kim, "Compensation of ESD and input capacitance effect by using package bondwire inductance for over gbps differential serdes devices," in Proc. Electr. Performance Electron. Packag., 2003, pp. 159-162.
17. D. G. Kam, H. Lee, and J. Kim, "Twisted differential line structure on high-speed printed circuit boards to reduce crosstalk and radiated emission," IEEE Trans. Adv. Packag., vol. 27, no. 4, pp. 590- 596, Nov.
18. J.-M. Jong and V. K. Tripathi, "Time-domain characterization of interconnect discontinuities in high-speed circuits," IEEE Trans. Comp. Hybrids Manufact. Technol., vol. 15, no. 4, pp. 497-504, Aug. 1992.
19. MJSQ-Methodologies for jitter and signal quality specification, part of the INCITS project T11.2 [Online]. Available: http://www.t11.org/ndex.htm