A parallel preconditioning strategy for efficient transistor-level circuit simulation

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2009, Pages 410-417

  Thornquist, Heidi K ^a   Keiter, Eric R ^a   Hoekstra, Robert J ^a   Day, David M ^a   Boman, Erik G ^a  

^a SANDIA NATIONAL LABORATORIES   (United States)

Author keywords

Circuit simulation; Hypergraph partitioning; Iterative matrix solvers; Multi core; Parallel simulation; Preconditioners

Indexed keywords

CIRCUIT SIMULATION; COMPUTER AIDED DESIGN; COMPUTER CIRCUITS; JACOBIAN MATRICES; MESSAGE PASSING; TIMING CIRCUITS;

HYPERGRAPH PARTITIONING; ITERATIVE MATRICES; MULTI CORE; PARALLEL SIMULATIONS; PRECONDITIONERS;

SPICE;

EID: 76349121999     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1687399.1687477     Document Type: Conference Paper

References (43)

1. Cadence UltraSim. http://www.cadence.com/products/custom-ic/ ultrasim/.
2. Nascentric OmegaSim. http://www.nascentric.com/omegasim-gx.html.
3. Synopsys HSIM. http://www.synopsys.com/products/mixedsignal/hsim/ hsim.html.
4. Synopsys NanoSim. http://www.synopsys.com/products/mixedsignal/ nanosim.
5. Xyce Parallel Circuit Simulator. http://xyce.sandia.gov.
6. P. Amestoy, T.Davis, and I.Duff. An approximate minimum degree ordering algorithm. SIAM J. Matrix Anal. Appl., 17(4):886-905, 1996.
7. J. Barby and R. Guindi. Circuitsim93: A circuit simulator benchmarking methodology case study. In Proceedings Sixth Annual IEEE International ASIC Conference and Exhibit, Rochester NY, 1993.
8. A. Basermann, U. Jaekel, and K. Hachiy. Preconditioning parallel sparse iterative solvers for circuit simulation. In Proceedings of the 8th SIAM Proceedings on Applied Linear Algebra, Williamsburg VA, 2003.
9. A. Basermann, U. Jaekel, and M. Nordhausen. Parallel iterative solvers for sparse linear systems in circuit simulation. Fut. Gen.. Comput. Sys., 21(8):1275-1284, 2005.
10. C. Bomhof and H. vanderVorst. A parallel linear system solver for circuit simulation problems. Num. Lin. Alg. Appl., 7(7-8):649-665, 2000.
11. Ü. Çatalyürek and C. Aykanat. Hypergraph-partitioning- based decomposition for parallel sparse-matrix vector multiplication. IEEE Trans. Parallel Dist. Systems, 10(7):673-693, 1999.
12. T. A. Davis. Direct Methods for Sparse Linear System. SIAM, 2006.
13. D. M. Day, M. K. Bhardwaj, G. M. Reese, and J. S. Peery. Mechanism free domain decomposition. Comput. Meth. Appl. Mech. Engrg., 182(7):763-776, 2005.
14. K. Devine, E. Boman, R. Heaphy, R. Bisseling, and U. Catalyurek. Parallel hypergraph partitioning for scientific computing. In Proc. of 20th International Parallel and Distributed Processing Symposium (IPDPS'06). IEEE, 2006.
15. L. Fleischer, B. Hendrickson, and A. Pinar. On identifying strongly connected components in parallel. In Proc. of IPDPS'00, LNCS 1800, pages 505-511. Springer, 2000.
16. N. Fröhlich, B. Riess, U. Wever, and Q. Zheng. A new approach for parallel simulation of vlsi-circuits on a transistor level. IEEE Transactions on Circuits and Systems Part I, 45(6):601-613, 1998.
17. W. Gropp, E. Lusk, N. Doss, and A. Skjellum. A high-performance, portable implementation of the MPI message passing interface standard. Parallel Computing, 22(6):789-828, Sept. 1996.
18. K. Gulati, J. F. Croix, S. P. Khatr, and R. Shastry. Fast circuit simulation on graphics processing units. In Proceedings of the 2009 Conference on Asia and South Pacific Design Automation, pages 403-408. IEEE Press, 2009.
19. B. Hendrickson and R. Leland. A multilevel algorithm for partitioning graphs. In Proc. Supercomputing '95. ACM, December 1995.
20. J. Huang, Z. Liu, M. Jeng, K. Hui, M. Chan, P. KO, and C. Hu. BSIM3 Manual. Technical report, Department of Electrical Engineering and Computer Science, University of California, Berkeley, CA 94720.
21. G. Karypis, R. Aggarwal, V. Kumar, and S. Shekhar. Multilevel hypergraph partitioning: Applications in VLSI domain. IEEE Trans. VLSI Systems, 20(1), 1999.
22. G. Karypis and V. Kumar. ParMETIS: Parallel graph partitioning and sparse matrix ordering library. Technical Report 97-060, CS Dept., Univ. Minn., 1997.
23. B. W. Kernighan and S. Lin. An efficient heuristic procedure for partitioning graphs. The Bell System Technical Journal, 49(2):291-307, 1970.
24. K. Kundert. Sparse matrix techniques. In A. Ruehli, editor, Circuit Analysis, Simulation and Design. North - Holland, 1987.
25. E. Lelarasmee, A. E. Ruehli, and A. L. Sangiovanni-Vincentelli. The waveform relaxation method for the time-domain analysis of large scale integrated circuits. IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., CAD-1(3):131-145, July 1982.
26. X. S. Li and J. W. Demmel. SuperLU DIST: A scalable distributed-memory sparse direct solver for unsymmetric linear systems. ACM Trans. Math. Softw., 29(2):110-140, 2003.
27. M. Heroux, et. al. An overview of the Trilinos project. ACM TOMS, 31(3):397-423, 2005. http://trilinos.sandia.gov.
28. F. Manne and R. H. Bisseling. A parallel approximation algorithm for the weighted maximum matching problem. In Proc. of PMAA'08, LNCS 4967, pages 708-717. Springer, Berlin, 2008.
29. W. McLendon, B. Hendrickson, S. Plimpton, and L. Rauchwerger. Finding strongly connected components in distributed graphs. J. of Parallel and Distributed Computing, 65:901-910, 2005.
30. L. W. Nagel. Spice 2, a computer program to simulate semiconductor circuits. Technical Report Memorandum ERL-M250, 1975.
31. J. N. K. S. R. Nassif and F. N. Najm. A multigrid-like technique for power grid analysis. IEEE Transactions on Computer-aided Design, 21:1148-1160, Oct. 2002.
32. A. R. Newton and A. L. Sangiovanni-Vincentelli. Relaxation based electrical simulation. IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., CAD-3(4):308-330, October 1984.
33. H. Peng and C.-K. Cheng. Parallel transistor level circuit simulation using domain decomposition methods. In Proceedings of the 2009 Conference on Asia and South Pacific Design Automation, pages 397-402. IEEE Press, 2009.
34. Y. Saad. Iterative Methods for Sparse Linear Systems. SIAM, Philadelphia, PA., second edition, 2003.
35. O. Schenk and K. Gärtner. Solving unsymmetric sparse systems of linear equations with PARDISO. Fut. Gen.. Comput. Sys., 20(3):475-487, 2005.
36. N. Selvakkumaran and G. Karypis. Multi-objective hypergraph partitioning algorithms for cut and maximum subdomain degree minimization. IEEE Transactions on Computer-Aided Design, 25(3):504-517, 2006.
37. K. Stanley and T. Davis. KLU: a 'Clark Kent' sparse LU factorization algorithm for circuit matrices. In SIAM Conference on Parallel Processing for Scientfic Computing (PP04), 2004.
38. P. Su, H. Wan, S. Fung, M. Chan, A. Niknejad, and C. Hu. BSIM3SOI3.1 MOSFET MODEL Users' Manual. Technical report, Department of Electrical Engineering and Computer Science, University of California, Berkeley, CA 94720.
39. K. Sun, Q. Zhou, K. Mohanram, and D. C. Sorensen. Parallel domain decomposition for simulation of large-scale power grids. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pages 54-59, November 2007.
40. B. Ucar and C. Aykanat. Partitioning sparse matrices for parallel preconditioned iterative methods. SIAM J. Sci. Comput., 29(4):1683-1709, 2007.
41. J. White and A. L. Sangiovanni-Vincentelli. Relax2: A new waveform relaxation approach for the analysis of lsi mos circuits. in Proc. Int. Symp. Circuits Syst., 2:756-759, May 1983.
42. J. K. White and A. Sangiovanni-Vincentelli. Relaxation techniques for the simulation of VLSI circuits. Kluwer Academic Publishers, 1987.
43. C. Zhuo, J. Hu, M. Zhao, and K. Chen. Power grid analysis and optimization using algebraic multigrid. IEEE Transactions on Computer-aided Design, 27:738-751, April 2008.