-
1
-
-
0026897113
-
"Algorithms for modern circuit simulation
-
vol. 46, pp. 274-285, 1992.
-
U. Feldmann, U. Wever, Q. Zheng, R. Schultz, and H. Wriedt, "Algorithms for modern circuit simulation,"Archiv für Elektronik und Übertragungstechnik AEÜ, vol. 46, pp. 274-285, 1992.
-
"Archiv Für Elektronik Und Übertragungstechnik AEÜ
-
-
Feldmann, U.1
Wever, U.2
Zheng, Q.3
Schultz, R.4
Wriedt, H.5
-
2
-
-
0028015493
-
"Parallel harmonic balance
-
Grenoble, 1993, pp. 251-260.
-
M. Schneider, U. Wever, and Q. Zheng, "Parallel harmonic balance," in IFIP Trans. A-42 VLSI'93, Grenoble, 1993, pp. 251-260.
-
" in IFIP Trans. A-42 VLSI'93
-
-
Schneider, M.1
Wever, U.2
Zheng, Q.3
-
3
-
-
0002293638
-
"Domain decomposition and parallel processing for the numerical solution of partial differential equations
-
pp. 75-118, 1991.
-
A. Quarteroni, "Domain decomposition and parallel processing for the numerical solution of partial differential equations,"Survey on Mathematics for Industry I, pp. 75-118, 1991.
-
"Survey on Mathematics for Industry I
-
-
Quarteroni, A.1
-
4
-
-
0017636064
-
"An efficient heuristic cluster algorithm for tearing large-scale networks
-
vol. CAS-24, no. 12, pp. 709-717, Dec. 1977.
-
A. Sangiovanni-Vincentelli, L.-K. Chen, and L. O. Chua, "An efficient heuristic cluster algorithm for tearing large-scale networks,"IEEE Trans. Circuits Syst., vol. CAS-24, no. 12, pp. 709-717, Dec. 1977.
-
"IEEE Trans. Circuits Syst.
-
-
Sangiovanni-Vincentelli, A.1
Chen, L.-K.2
Chua, L.O.3
-
5
-
-
84893678595
-
"Waveform techniques
-
Vol. 3. A. E. Ruehli, Ed. Amsterdam, The Netherlands: Elsevier Science Publishers B.V., 1985, pp. 41-127.
-
P. Debefve, F. Odeh, and A. E. Ruehli, "Waveform techniques," in Circuit Analysis, Simulation and Design, Part 2, Advances in CAD for VLSI, Vol. 3. A. E. Ruehli, Ed. Amsterdam, The Netherlands: Elsevier Science Publishers B.V., 1985, pp. 41-127.
-
" in Circuit Analysis, Simulation and Design, Part 2, Advances in CAD for VLSI
-
-
Debefve, P.1
Odeh, F.2
Ruehli, A.E.3
-
7
-
-
0022984561
-
"Circuit partitioning for parallel processing
-
1986, pp. 186-189.
-
P. Cox, R. Burch, and B. Epler, "Circuit partitioning for parallel processing," in Proc. IEEE/ACM Int. Conf. Computer-Aided Design (ICCAD), 1986, pp. 186-189.
-
" in Proc. IEEE/ACM Int. Conf. Computer-Aided Design (ICCAD)
-
-
Cox, P.1
Burch, R.2
Epler, B.3
-
8
-
-
0027091235
-
"Circuit partitioning for waveform relaxation
-
Amsterdam, The Netherlands, Feb. 1991, pp. 149-153.
-
W. John, W. Rissiek, and K. L. Paap, "Circuit partitioning for waveform relaxation," in Proc. Eur. Conf. Design Automation (EDAC), Amsterdam, The Netherlands, Feb. 1991, pp. 149-153.
-
" in Proc. Eur. Conf. Design Automation (EDAC)
-
-
John, W.1
Rissiek, W.2
Paap, K.L.3
-
9
-
-
0028396574
-
"A circuit partitioning approach for parallel circuit simulation
-
vol. E77-A, no. 3, pp. 461-466, 1994.
-
T. Kage, F. Kawafuji, and J. Niitsuma, "A circuit partitioning approach for parallel circuit simulation,"IEICE Trans. Fundamentals, vol. E77-A, no. 3, pp. 461-466, 1994.
-
"IEICE Trans. Fundamentals
-
-
Kage, T.1
Kawafuji, F.2
Niitsuma, J.3
-
10
-
-
0026174925
-
"Analytical placement: A linear or a quadratic objective function?
-
1991, pp. 427-432.
-
G. Sigl, K. Doll, and F. M. Johannes, "Analytical placement: A linear or a quadratic objective function?," in Proc. ACM/IEEE Design Automation Conf. (DAC), San Francisco, CA, 1991, pp. 427-432.
-
" in Proc. ACM/IEEE Design Automation Conf. (DAC), San Francisco, CA
-
-
Sigl, G.1
Doll, K.2
Johannes, F.M.3
-
12
-
-
0027060021
-
"Fast spectral methods for ratio cut partitioning and clustering
-
1991, pp. 10-13.
-
_, "Fast spectral methods for ratio cut partitioning and clustering," in Proc. IEEE/ACM Int. Conf. Computer-Aided Design (ICCAD), 1991, pp. 10-13.
-
" in Proc. IEEE/ACM Int. Conf. Computer-Aided Design (ICCAD)
-
-
-
13
-
-
0028554371
-
"Partitioning very large circuits using analytical placement techniques
-
1994, pp. 646-651.
-
B. M. Riess, K. Doll, and F. M. Johannes, "Partitioning very large circuits using analytical placement techniques," in Proc. ACM/IEEE Design Automation Conf. (DAC), June, 1994, pp. 646-651.
-
" in Proc. ACM/IEEE Design Automation Conf. (DAC), June
-
-
Riess, B.M.1
Doll, K.2
Johannes, F.M.3
-
15
-
-
47949098295
-
"Domain decomposition methods for circuit simulation
-
1994, pp. 183-186.
-
U. Kleis, O. Wallat, U. Wever, and Q. Zheng, "Domain decomposition methods for circuit simulation," in Proc. ACM/SCS/IEEE Workshop Parallel and Distributed Simulation (PADS), 1994, pp. 183-186.
-
" in Proc. ACM/SCS/IEEE Workshop Parallel and Distributed Simulation (PADS)
-
-
Kleis, U.1
Wallat, O.2
Wever, U.3
Zheng, Q.4
-
16
-
-
33747814335
-
"Parallel circuit simulation on workstation clusters
-
94. H. Neunzert, Ed. New York: Wiley, 1994, pp. 274-284.
-
U. Wever and Q. Zheng, "Parallel circuit simulation on workstation clusters," in Progress in Industrial Mathematics at ECMI94. H. Neunzert, Ed. New York: Wiley, 1994, pp. 274-284.
-
" in Progress in Industrial Mathematics at ECMI
-
-
Wever, U.1
Zheng, Q.2
-
17
-
-
51549120883
-
"Parallel transient analysis for circuit simulation
-
29th Annu. Hawaii Int. Conf. System Sciences, 1996, vol. 1, pp. 442-447.
-
_, "Parallel transient analysis for circuit simulation," in Proc. 29th Annu. Hawaii Int. Conf. System Sciences, 1996, vol. 1, pp. 442-447.
-
" in Proc.
-
-
-
18
-
-
84990891523
-
"Architecture driven K-way partitioning for multichip modules
-
1995, pp. 71-75.
-
B. M. Riess and A. A. Schoene, "Architecture driven K-way partitioning for multichip modules," in Proc. Euro. Design and Test Conf. (ED&TC), Paris, France, Mar. 1995, pp. 71-75.
-
" in Proc. Euro. Design and Test Conf. (ED&TC), Paris, France, Mar.
-
-
Riess, B.M.1
Schoene, A.A.2
-
19
-
-
0004001955
-
-
2: A computer program to simulate semiconductor circuits," Ph.D. dissertation, Univ. of California, Berkeley, 1975.
-
L. Nagel, "SPICE2: A computer program to simulate semiconductor circuits," Ph.D. dissertation, Univ. of California, Berkeley, 1975.
-
"SPICE
-
-
Nagel, L.1
-
20
-
-
0029542930
-
"Linear decomposition algorithm for VLSI design applications
-
1995, pp. 223-228.
-
J. Li, J. Lillis, and C.-K. Cheng, "Linear decomposition algorithm for VLSI design applications," in Proc. IEEE/ACM Int. Conf. Computer-Aided Design (ICCAD), Nov. 1995, pp. 223-228.
-
" in Proc. IEEE/ACM Int. Conf. Computer-Aided Design (ICCAD), Nov.
-
-
Li, J.1
Lillis, J.2
Cheng, C.-K.3
-
22
-
-
0026191188
-
"Ratio cut partitioning for hierarchical designs
-
vol. CAD-10, no. 7, pp. 911-921, July 1991.
-
_, "Ratio cut partitioning for hierarchical designs,"IEEE Trans. Computer-Aided Design, vol. CAD-10, no. 7, pp. 911-921, July 1991.
-
"IEEE Trans. Computer-Aided Design
-
-
-
23
-
-
0023979261
-
"An algorithm for quadrisection and its application to standard cell placement
-
vol. CAS-35, no. 3, pp. 294-303, Mar. 1988.
-
P. R. Suaris and G. Kedem, "An algorithm for quadrisection and its application to standard cell placement,"IEEE Trans. Circuits Syst., vol. CAS-35, no. 3, pp. 294-303, Mar. 1988.
-
"IEEE Trans. Circuits Syst.
-
-
Suaris, P.R.1
Kedem, G.2
-
24
-
-
0018522050
-
"A multilevel Newton algorithm with macromodeling and latency for the analysis of large-scale nonlinear circuits in the time domain
-
pp. 733-741, 1979.
-
N. B. G. Rabbat, A. L. Sangiovanni-Vincentelli, and H. Y. Hsieh, "A multilevel Newton algorithm with macromodeling and latency for the analysis of large-scale nonlinear circuits in the time domain,"IEEE Trans. Circuits Syst., pp. 733-741, 1979.
-
"IEEE Trans. Circuits Syst.
-
-
Rabbat, N.B.G.1
Sangiovanni-Vincentelli, A.L.2
Hsieh, H.Y.3
-
25
-
-
0003798597
-
-
Tennessee: Oak Ridge National Laboratory, 1993.
-
A. Geist, A. Beguelin, J. Dongarra, W. Jiang, R. Manchek, and V. Sunderam, PVM 3.0 User's Guide and Reference Manual. Tennessee: Oak Ridge National Laboratory, 1993.
-
PVM 3.0 User's Guide and Reference Manual.
-
-
Geist, A.1
Beguelin, A.2
Dongarra, J.3
Jiang, W.4
Manchek, R.5
Sunderam, V.6
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