Novel hardware processing unit for dynamic on-line entropy estimation of discrete time information

Digital Signal Processing: A Review Journal

Volumn 20, Issue 2, 2010, Pages 337-346

  Cabal Yepez, E ^a   Romero Troncoso, R de J ^a   Garcia Perez, A ^a   Rodriguez Donate, C ^a  

^a UNIVERSITY OF GUANAJUATO   (Mexico)

Author keywords

Broken bar detection; Entropy estimation; Fast architecture; Field programmable gate arrays

Indexed keywords

FIELD PROGRAMMABLE GATE ARRAYS (FPGA); HARDWARE; INDUCTION MOTORS;

BROKEN BAR DETECTION; ENTROPY ESTIMATION; FPGA IMPLEMENTATIONS; HARDWARE STRUCTURES; INFORMATION CONTENTS; INFORMATION ENTROPY; ORDERS OF MAGNITUDE; PROPOSED ARCHITECTURES;

MEMORY ARCHITECTURE;

EID: 76349113582     PISSN: 10512004     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.dsp.2009.06.012     Document Type: Article

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