An entropy-based learning hardware organization using FPGA

Proceedings of the Annual Southeastern Symposium on System Theory

Volumn 2001-January, Issue , 2001, Pages 209-213

  Starzyk, J ^a   Guo, Yongtao ^a  

^a Ohio University   (United States)

Author keywords

Algorithm design and analysis; Arithmetic; Artificial neural networks; Biological neural networks; Circuits; Computer architecture; Entropy; Field programmable gate arrays; Hardware; Training data

Indexed keywords

BIOINFORMATICS; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; DESIGN; DIGITAL ARITHMETIC; ENTROPY; HARDWARE; INTEGRATED CIRCUIT DESIGN; NETWORKS (CIRCUITS); NEURAL NETWORKS; SYSTEM BUSES; SYSTEM THEORY;

ALGORITHM DESIGN AND ANALYSIS; BIOLOGICAL NEURAL NETWORKS; DMA TRANSFERS; ENTROPY-BASED; FPGA IMPLEMENTATIONS; NEURAL NETWORK MODEL; PCI BUS INTERFACE; TRAINING DATA;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 84949977207     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SSST.2001.918519     Document Type: Conference Paper

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