The entropy of FPGA reconfiguration

Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL

Volumn , Issue , 2006, Pages 261-266

  Malik, Usama ^a,b   Diessel, Oliver ^a,b  

^a UNIVERSITY OF NEW SOUTH WALES   (Australia)

^b CSIRO   (Australia)

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARKING; ENTROPY; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); FUZZY LOGIC; NETWORKS (CIRCUITS); VECTORS;

AMOUNT OF INFORMATION; BENCHMARK CIRCUITS; CHIP AREAS; COMPRESSION TECHNIQUES; CONFIGURATION MEMORY; FIELD PROGRAMMABLE LOGIC (FPL); IN LINE; INTERNATIONAL CONFERENCES;

DATA COMPRESSION;

EID: 34547485677     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2006.311223     Document Type: Conference Paper

References (9)

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9. U. Malik and O. Diessel, "A configuration memory architecture for fast FPGA reconfiguration," Technical Report UNSW-CSE-TR0509, 2005.