Post-placement interconnect entropy

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 15, Issue 8, 2007, Pages 945-948

  Feng, Wenyi ^a   Greene, Jonathan W ^a  

^a Actel Corp   (United States)

Author keywords

Entropy; Field programmable gate array (FPGA); Interconnections; Placement; Programmable logic device (PLD)

Indexed keywords

COMPUTER ARCHITECTURE; INTERCONNECTION NETWORKS; NUMERICAL METHODS; OPTIMIZATION; PROGRAMMABLE LOGIC CONTROLLERS; TABLE LOOKUP;

CONFIGURATION BITS; INTERCONNECTIONS; PROGRAMMABLE LOGIC DEVICES (PLD);

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 34547440188     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2007.900747     Document Type: Conference Paper

References (16)

1. V. Betz, J. Rose, and A. Marquardt, Architecture and CAD for Deep-Submicmn FPGAs. Norwell, MA: Kluwer, 1999.
2. G. Lemieux and D. Lewis, Design of Interconnection Networksfor Programmable Logic. Norwell, MA: Kluwer, 2004.
3. W. E. Donath, "Placement and average interconnection lengths of computer logic," IEEE Trans. Circuits Syst., vol. CAS-26, no. 4, pp. 272-277, Apr. 1979.
4. U. Malik and O. Diessel, "The entropy of FPGA configuration," in Proc. FPL, 2006, pp. 261-266.
5. A. DeHon, "Rent's rule based switching requirements," in Proc. SLIP, 2001, pp. 197-204.
6. R. Rubin and A. Dehon, "Design of FPGA interconnect for multilevel metallization," in Proc. Int. Symp. FGPAs, 2003, pp. 154-163.
7. A. DeHon, "Entropy, counting, and programmable interconnect," in Proc. Int. Symp. FGPAs, 1996, pp. 73-79.
8. Y. Matsumoto and A. Masaki, "FPGAs with multidimensional switch topology," IEICE Trans. Inf. Syst., vol. E88-D, pp. 775-778, Apr. 2005.
9. H. Schmit, "Extra dimensional island style FPGAs," in Proc. Field Program. Logic Appl. (FPL), 2003, pp. 406-415.
10. C. E. Shannon, "A mathematical theory of communication," Bell Syst. Tech. J., vol. 27, pp. 379-423, Jul./Oct. 1948.
11. B. S. Landman and R. L. Russo, "On a pin versus block relationship for partitions of logic graphs," IEEE Trans. Comput., vol. C-20, no. 12, pp. 1469-1479, Dec. 1971.
12. W. E. Donath, "Wire length, distribution for placements of computer logic," IBM J. Res. Develop., vol. 25, pp. 152-155, May 1981.
13. D. Stroobandt, A Priori Wire Length Estimates for Digital Design. Norwell, MA: Kluwer, 2001.
14. D. Stroobandt, "Multi-terminal nets do change conventional wire length, distribution models," in Proc. SLIP, 2001, pp. 41-48.
15. W. Feng and J. Greene, "Post-placement interconnect entropy: How many configuration bits does a PLD need'?," in Proc. Syst.-Level Interconnect Prediction (SLIP), 2006, pp. 41-48.
16. T. Cover and J. Thomas, Elements of Information Theory. New York: Wiley, 1991.