FPGA placement by thermodynamic combinatorial optimization

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2002, Pages 54-60

  De Vicente, Juan ^a   Lanchares, Juan ^b   Hermida, Román ^b  

^a Electrotechnical Section   (Spain)

^b UNIVERSIDAD COMPLUTENSE DE MADRID   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARK CIRCUIT; FERMI-DIRAC STATISTICS; MACRO-STATE; PLACEMENT PROBLEMS; REVERSIBLE TRANSFORMATION; SHANNON; THERMODYNAMIC LAWS; TIME REDUCTION;

COMBINATORIAL OPTIMIZATION; EXHIBITIONS; SIMULATED ANNEALING;

THERMODYNAMICS;

EID: 3042663829     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2002.998249     Document Type: Conference Paper

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