Testing circuit-partitioned 3D IC designs

Proceedings of the 2009 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2009

Volumn , Issue , 2009, Pages 139-144

  Lewis, Dean L ^a   Lee, Hsien Hsin S ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

3D ICs; BIST; DFT; Die stacking; Memory test

Indexed keywords

3D ICS; BIST; DFT; DIE STACKING; MEMORY TEST;

COMPUTER ARCHITECTURE; DIES; MICROPROCESSOR CHIPS; PROBABILITY DENSITY FUNCTION; THREE DIMENSIONAL;

TESTING;

EID: 70349495477     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISVLSI.2009.48     Document Type: Conference Paper

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