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Volumn , Issue , 2009, Pages 141-144

A 6bit, 7mW, 250fJ, 700MS/s subranging ADC

Author keywords

[No Author keywords available]

Indexed keywords

90NM CMOS; INPUT FREQUENCY; LOW POWER; NYQUIST; WEIGHTED INTERPOLATION;

EID: 76249121480     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASSCC.2009.5357198     Document Type: Conference Paper
Times cited : (21)

References (13)
  • 1
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    • Chen, C.-Y.1    Le, M.2    Kim, K.-Y.3
  • 3
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    • Nov
    • F. C. Hsieh and T. C. Lee, "A 6-bit Pipelined Analog-to Digital Converter with Current-Switching Open-Loop Residue Amplification," in Proc. IEEE A-SSCC, pp. 61-64, Nov. 2008.
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    • Hsieh, F.C.1    Lee, T.C.2
  • 4
    • 49549116231 scopus 로고    scopus 로고
    • A 32mW 1.25GS/S 6b 2b-step SAR. ADC in 0.13um CMOS
    • Feb
    • Z. Cao, S. Yan, and Y. Li, "A 32mW 1.25GS/S 6b 2b-step SAR. ADC in 0.13um CMOS," in ISSCC Dig. Tech. papers, pp. 542-543, Feb. 2008.
    • (2008) ISSCC Dig. Tech. Papers , pp. 542-543
    • Cao, Z.1    Yan, S.2    Li, Y.3
  • 5
    • 49549115760 scopus 로고    scopus 로고
    • A 24GS/S 6b ADC in 90nm CMOS
    • Feb
    • P. Schvan, et al., "A 24GS/S 6b ADC in 90nm CMOS," in ISSCC, Dig. of Tech. Papers, pp.544-545, Feb. 2008.
    • (2008) ISSCC, Dig. of Tech. Papers , pp. 544-545
    • Schvan, P.1
  • 6
    • 67649977039 scopus 로고    scopus 로고
    • A 6-b 1-GS/s 30-mW ADC in 90-nm CMOS technology
    • Nov
    • Y. C. Lien and J. Lee, "A 6-b 1-GS/s 30-mW ADC in 90-nm CMOS Technology," in Proc. IEEE A-SSCC, pp. 45-48, Nov. 2008.
    • (2008) Proc. IEEE A-SSCC , pp. 45-48
    • Lien, Y.C.1    Lee, J.2
  • 7
    • 49549089559 scopus 로고    scopus 로고
    • A 2.2:mW 5b 1.75GS/S folding flash ADC in 90nm digital. CMOS
    • Feb
    • B. Verbruggen, et al. , "A 2.2:mW 5b 1.75GS/S Folding Flash ADC in 90nm Digital. CMOS," in ISSCC Dig. Tech. papers, pp. 252-253, Feb. 2008.
    • (2008) ISSCC Dig. Tech. Papers , pp. 252-253
    • Verbruggen, B.1
  • 8
    • 57849087345 scopus 로고    scopus 로고
    • A 52mW 10b 210MS/8 two-step ADC for digital-IF receivers in 0.13um CMOS
    • Sep
    • Z. Cao and S. Yan, "A 52mW 10b 210MS/8 Two-Step ADC for Digital-IF Receivers in 0.13um CMOS," in Dig. of CICC, pp. 309-312, Sep. 2008.
    • (2008) Dig. of CICC , pp. 309-312
    • Cao, Z.1    Yan, S.2
  • 9
    • 0025450133 scopus 로고
    • A 10b 30MHz two-step parallel BiCMOS ADC with internal S/H
    • Feb
    • A. Matsuzawa, et al., "A 10b 30MHz Two-Step parallel BiCMOS ADC with internal S/H," in ISSCC Dig. Tech. papers, pp. 162-163, Feb. 1990.
    • (1990) ISSCC Dig. Tech. Papers , pp. 162-163
    • Matsuzawa, A.1
  • 10
    • 67649933801 scopus 로고    scopus 로고
    • A 770-MHz, 70mW, 8-bit subranging ADC using reference voltage precharging architecture
    • Nov
    • K. Ohhata, et al., "A 770-MHz, 70mW, 8-bit Subranging ADC using Reference Voltage Precharging Architecture," in Proc. IEEE A-SSCC, pp. 41-44, Nov. 2008.
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    • Ohhata, K.1
  • 11
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    • Nov
    • M. Miyahara, Y. Asada, D. Paik, and A. Matsuzawa, "A Low-Noise Self Calibrating Dynamic Comparator for High-Speed ADCs," in Proc. IEEE A-SSCC, pp. 269-272, Nov. 2008.
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    • Miyahara, M.1    Asada, Y.2    Paik, D.3    Matsuzawa, A.4
  • 13
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    • Giannini, V.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.