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1
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51949115762
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A low power 6-bit flash ADC with reference voltage and common-mode calibration
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June
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C-Y. Chen, M. Le, and K-Y. Kim, "A Low Power 6-bit Flash ADC with Reference Voltage and Common-Mode Calibration," in Dig. Symp. VLSI Circuits, pp.12-13, June, 2008.
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Dig. Symp. VLSI Circuits
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Chen, C.-Y.1
Le, M.2
Kim, K.-Y.3
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2
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67649983276
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A 6-bit, 1.2-GS/s ADC with wideband THA in 0.13-um CMOS
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Nov
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B-W. Chen, S-K. Hsien, C-S. Chiang, and. K-C. Juang, "A 6-Bit, 1.2-GS/s ADC with Wideband THA in 0.13-um CMOS," in Proc. IEEE A-SSCC, pp. 381-384, Nov. 2008.
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Proc. IEEE A-SSCC
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Chen, B.-W.1
Hsien, S.-K.2
Chiang, C.-S.3
Juang, K.-C.4
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3
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67649992723
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A 6-bit pipelined analog-to digital converter with current-switching open-loop residue amplification
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Nov
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F. C. Hsieh and T. C. Lee, "A 6-bit Pipelined Analog-to Digital Converter with Current-Switching Open-Loop Residue Amplification," in Proc. IEEE A-SSCC, pp. 61-64, Nov. 2008.
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Proc. IEEE A-SSCC
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Hsieh, F.C.1
Lee, T.C.2
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4
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49549116231
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A 32mW 1.25GS/S 6b 2b-step SAR. ADC in 0.13um CMOS
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Feb
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Z. Cao, S. Yan, and Y. Li, "A 32mW 1.25GS/S 6b 2b-step SAR. ADC in 0.13um CMOS," in ISSCC Dig. Tech. papers, pp. 542-543, Feb. 2008.
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ISSCC Dig. Tech. Papers
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Cao, Z.1
Yan, S.2
Li, Y.3
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5
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49549115760
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A 24GS/S 6b ADC in 90nm CMOS
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Feb
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P. Schvan, et al., "A 24GS/S 6b ADC in 90nm CMOS," in ISSCC, Dig. of Tech. Papers, pp.544-545, Feb. 2008.
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ISSCC, Dig. of Tech. Papers
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Schvan, P.1
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6
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67649977039
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A 6-b 1-GS/s 30-mW ADC in 90-nm CMOS technology
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Nov
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Y. C. Lien and J. Lee, "A 6-b 1-GS/s 30-mW ADC in 90-nm CMOS Technology," in Proc. IEEE A-SSCC, pp. 45-48, Nov. 2008.
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Proc. IEEE A-SSCC
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Lien, Y.C.1
Lee, J.2
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7
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49549089559
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A 2.2:mW 5b 1.75GS/S folding flash ADC in 90nm digital. CMOS
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Feb
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B. Verbruggen, et al. , "A 2.2:mW 5b 1.75GS/S Folding Flash ADC in 90nm Digital. CMOS," in ISSCC Dig. Tech. papers, pp. 252-253, Feb. 2008.
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ISSCC Dig. Tech. Papers
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Verbruggen, B.1
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8
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57849087345
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A 52mW 10b 210MS/8 two-step ADC for digital-IF receivers in 0.13um CMOS
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Sep
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Z. Cao and S. Yan, "A 52mW 10b 210MS/8 Two-Step ADC for Digital-IF Receivers in 0.13um CMOS," in Dig. of CICC, pp. 309-312, Sep. 2008.
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Dig. of CICC
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Cao, Z.1
Yan, S.2
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9
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0025450133
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A 10b 30MHz two-step parallel BiCMOS ADC with internal S/H
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Feb
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A. Matsuzawa, et al., "A 10b 30MHz Two-Step parallel BiCMOS ADC with internal S/H," in ISSCC Dig. Tech. papers, pp. 162-163, Feb. 1990.
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ISSCC Dig. Tech. Papers
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Matsuzawa, A.1
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10
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67649933801
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A 770-MHz, 70mW, 8-bit subranging ADC using reference voltage precharging architecture
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Nov
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K. Ohhata, et al., "A 770-MHz, 70mW, 8-bit Subranging ADC using Reference Voltage Precharging Architecture," in Proc. IEEE A-SSCC, pp. 41-44, Nov. 2008.
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Proc. IEEE A-SSCC
, pp. 41-44
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Ohhata, K.1
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11
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67649921302
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A low-noise self calibrating dynamic comparator for high-speed ADCs
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Nov
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M. Miyahara, Y. Asada, D. Paik, and A. Matsuzawa, "A Low-Noise Self Calibrating Dynamic Comparator for High-Speed ADCs," in Proc. IEEE A-SSCC, pp. 269-272, Nov. 2008.
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Proc. IEEE A-SSCC
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Miyahara, M.1
Asada, Y.2
Paik, D.3
Matsuzawa, A.4
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13
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49549118053
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An 820μW 9b 40MS/S noise tolerant dynamicSAR ADC in 90nm digital CMOS
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V. Giannini, et al., "An 820μW 9b 40MS/S Noise Tolerant DynamicSAR ADC in 90nm Digital CMOS," in IEEE ISSCC 2008, Dig. of Tech. Papers, pp.238-239, Feb. 2008.
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IEEE ISSCC 2008, Dig. of Tech. Papers
, pp. 238-239
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Giannini, V.1
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