A real-time programmable LDPC decoder chip for arbitrary QC-LDPC parity check matrices

Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009

Volumn , Issue , 2009, Pages 369-372

  Shih, Xin Yu ^a   Zhan, Cheng Zhou ^a   Wu, An Yeu ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

Low power; Programmability; QC LDPC

Indexed keywords

BLOCK SIZES; CHANNEL ADAPTIVE; CMOS TECHNOLOGY; CODE RATES; CODEWORD LENGTH; DESIGN TECHNIQUE; DIE AREA; EARLY TERMINATION; HARDWARE ARCHITECTURE; INFORMATION BIT; LDPC DECODER; LOW POWER; PARITY CHECK MATRICES; PROGRAMMABILITY; PROTOTYPING; QUASI-CYCLIC; WORD LENGTH;

CMOS INTEGRATED CIRCUITS; COMMUNICATION SYSTEMS; CONVOLUTIONAL CODES; DECODING; MATRIX ALGEBRA; QUANTUM THEORY;

REAL TIME SYSTEMS;

EID: 76249091354     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASSCC.2009.5357173     Document Type: Conference Paper

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