-
1
-
-
33644661238
-
Content-addressable memory (CAM) circuits and architectures: A tutorial and survey
-
Mar.
-
K. Pagiamtzis and A. Sheikholeslami, "Content-addressable memory (CAM) circuits and architectures: A tutorial and survey," IEEE J. Solid-State Circuits, vol.41, no.3, pp. 712-727, Mar. 2006.
-
(2006)
IEEE J. Solid-State Circuits
, vol.41
, Issue.3
, pp. 712-727
-
-
Pagiamtzis, K.1
Sheikholeslami, A.2
-
2
-
-
34548751671
-
High performance database searching with HMMer on FPGAs
-
Mar.
-
T. Oliver, L. Y. Yeow, and B. Schmidt, "High performance database searching with HMMer on FPGAs," in Proc. IEEE Int. Parallel Distrib. Process. Symp., Mar. 2007, pp. 1-7.
-
(2007)
Proc. IEEE Int. Parallel Distrib. Process. Symp.
, pp. 1-7
-
-
Oliver, T.1
Yeow, L.Y.2
Schmidt, B.3
-
3
-
-
67649834408
-
Multilingual names database searching enhancement
-
Dec.
-
I. R. Draganov, A. A. Popova, and L. L. Ivanov, "Multilingual names database searching enhancement," in Proc. IEEE Int. Symp. Signal Process. Inf. Technol., Dec. 2008, pp. 474-479.
-
(2008)
Proc. IEEE Int. Symp. Signal Process. Inf. Technol.
, pp. 474-479
-
-
Draganov, I.R.1
Popova, A.A.2
Ivanov, L.L.3
-
4
-
-
62349096876
-
Towards an ultra-low power, high density and non-volatile ternary CAM
-
Dec.
-
M. El Baraji, V. Javerliac, and G. Prenat, "Towards an ultra-low power, high density and non-volatile ternary CAM," in Proc. 9th Annu. Non-Volatile Memory Technol. Symp., Dec. 2008, pp. 1-7.
-
(2008)
Proc. 9th Annu. Non-Volatile Memory Technol. Symp.
, pp. 1-7
-
-
El Baraji, M.1
Javerliac, V.2
Prenat, G.3
-
5
-
-
0035369412
-
A design for high-speed lowpower CMOS fully parallel content-addressable memory macros
-
Dec.
-
H. Miyatake, M. Tanaka, and Y. Mori, "A design for high-speed lowpower CMOS fully parallel content-addressable memory macros," IEEE J. Solid-State Circuits, vol.36, no.5, pp. 956-968, Dec. 2001.
-
(2001)
IEEE J. Solid-State Circuits
, vol.36
, Issue.5
, pp. 956-968
-
-
Miyatake, H.1
Tanaka, M.2
Mori, Y.3
-
6
-
-
0037389024
-
A low power precomputationbased fully parallel content-addressable memory
-
Apr.
-
C.-S. Lin, J.-C. Chang, and B.-D. Liu, "A low power precomputationbased fully parallel content-addressable memory," IEEE J. Solid-State Circuits, vol.38, no.4, pp. 654-662, Apr. 2003.
-
(2003)
IEEE J. Solid-State Circuits
, vol.38
, Issue.4
, pp. 654-662
-
-
Lin, C.-S.1
Chang, J.-C.2
Liu, B.-D.3
-
7
-
-
0242551718
-
A mismatch-dependent power allocation technique for match-line sensing in content-addressable memories
-
Nov.
-
I. Arsovski and A. Sheikholeslami, "A mismatch-dependent power allocation technique for match-line sensing in content-addressable memories," IEEE J. Solid-State Circuits, vol.38, no.11, pp. 1958-1966, Nov. 2003.
-
(2003)
IEEE J. Solid-State Circuits
, vol.38
, Issue.11
, pp. 1958-1966
-
-
Arsovski, I.1
Sheikholeslami, A.2
-
8
-
-
23744465803
-
A low-power CAM using pulsed NAND-NOR match-line and charge-recycling search-line driver
-
Aug.
-
B. D. Yang and L. S. Kim, "A low-power CAM using pulsed NAND-NOR match-line and charge-recycling search-line driver," IEEE J. Solid-State Circuits, vol.40, no.8, pp. 736-1744, Aug. 2005.
-
(2005)
IEEE J. Solid-State Circuits
, vol.40
, Issue.8
, pp. 736-1744
-
-
Yang, B.D.1
Kim, L.S.2
-
9
-
-
38849084539
-
A 0.2 V, 480 kb subthreshold SRAM with 1 k cells per bitline for ultra-low-voltage computing
-
Feb.
-
T. H. Kim, J. Liu, J. Keane, and C. H. Kim, "A 0.2 V, 480 kb subthreshold SRAM with 1 k cells per bitline for ultra-low-voltage computing," IEEE J. Solid-State Circuits, vol.43, no.2, pp. 518-529, Feb. 2008.
-
(2008)
IEEE J. Solid-State Circuits
, vol.43
, Issue.2
, pp. 518-529
-
-
Kim, T.H.1
Liu, J.2
Keane, J.3
Kim, C.H.4
-
10
-
-
4344578575
-
Static divided word matching line for low-power content addressable memory design
-
May
-
K.-H. Cheng, C.-H. Wei, and S.-Y. Jiang, "Static divided word matching line for low-power content addressable memory design," in Proc. IEEE Int. Symp. Circuits Syst., May 2004, vol.2, pp. 629-632.
-
(2004)
Proc. IEEE Int. Symp. Circuits Syst.
, vol.2
, pp. 629-632
-
-
Cheng, K.-H.1
Wei, C.-H.2
Jiang, S.-Y.3
-
11
-
-
39749103465
-
Low power design of precomputation-based content-addressable memory
-
Mar.
-
S. J. Ruan, C. Y. Wu, and J. Y. Hsieh, "Low power design of precomputation-based content-addressable memory," IEEE Trans. Very Large Scale Integr.(VLSI) Syst., vol.16, no.3, pp. 331-335, Mar. 2008.
-
(2008)
IEEE Trans. Very Large Scale Integr.(VLSI) Syst.
, vol.16
, Issue.3
, pp. 331-335
-
-
Ruan, S.J.1
Wu, C.Y.2
Hsieh, J.Y.3
-
12
-
-
51049089295
-
A versatile content addressable memory architecture
-
Mar.
-
X. Yang, S. Sezer, J. McCanny, and D. Burns, "A versatile content addressable memory architecture," in Proc. IEEE Int. SOC Conf.,Mar. 2007, pp. 215-218.
-
(2007)
Proc. IEEE Int. SOC Conf.
, pp. 215-218
-
-
Yang, X.1
Sezer, S.2
McCanny, J.3
Burns, D.4
-
13
-
-
50949119433
-
Novel content addressable memory architecture for adaptive systems
-
Aug.
-
X. Yang, S. Sezer, J. McCanny, and D. Burns, "Novel content addressable memory architecture for adaptive systems," in Proc. 2nd NASA/ESA Conf. Adapt. Hardw. Syst., Aug. 2007, pp. 633-640.
-
(2007)
Proc. 2nd NASA/ESA Conf. Adapt. Hardw. Syst.
, pp. 633-640
-
-
Yang, X.1
Sezer, S.2
McCanny, J.3
Burns, D.4
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