Novel content addressable memory architecture for adaptive systems

Proceedings - 2007 NASA/ESA Conference on Adaptive Hardware and Systems, AHS-2007

Volumn , Issue , 2007, Pages 633-638

  Yang, Xin ^a   Sezer, Sakir ^a   McCanny, John ^a   Burns, Dwayne ^a  

^a QUEEN'S UNIVERSITY BELFAST   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

CAMS; COMPUTER NETWORKS; DATA STORAGE EQUIPMENT; DIGITAL STORAGE;

CAM CELL; CONTENT-ADDRESSABLE MEMORY; ESSENTIAL COMPONENTS; NETWORK PROCESSING SYSTEMS;

ADAPTIVE SYSTEMS;

EID: 50949119433     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/AHS.2007.79     Document Type: Conference Paper

References (14)

1. Chi-Sheng Lin, Kuan-Hua Chen, and Bin-Da Liu, "Low-Power and Low-Voltage Fully Parallel Content-Addressable Memory", Proceedings of the 2003 International Symposium on Circuits and Systems, Vol.5, May 2003, pp. V-373-V376.
2. th IEEE International Midwest Symposium on Circuits and Systems, Vol. 3, Dec. 2003, pp. 1447-1450.
3. I. Arsovski, T. Chandler, and A. Sheikholeslami, "A Ternary Content Addressable Memory (TCAM) Based on 4T Static Storage and Including a Current-Race Sensing Scheme", IEEE Journal of Solid-State Circuits, Vol.38, No.1, Jan. 2003, pp. 155-158.
4. rd ACM/IEEE Design Automation Conference, July 2006, pp. 779-784.
5. N. Mohan and M. Sachdev, "Novel Ternary Storage Cells and Techniques for Leakage Reduction in Ternary CAM", IEEE International SOC Conference, Sept. 2006, pp. 311-314.
6. G. Kasai, Y. Takarabe, K. Furumi, and M. Yoneda, "200MHz/200MSPS 3.2W at 1.5V Vdd, 9.4Mbits Ternary CAM with New Charge Injection Match Detect Circuits and Bank Selection Scheme", IEEE Custom Integrated Circuits Conference, 2003, pp. 387-390.
7. R.A. Kempke and A.J. McAuley, "Ternary CAM Memory Architecture and Methodology", United States Patent 5,841,874, Aug. 1996.
8. S. Choi, K. Sohn, and H. Yoo, "A 0.7-fJ/Bit/Search 2.2-ns Search Time Hybrid-Type TCAM Architecture", IEEE Journal of Solid-State Circuits, Vol. 40, No. 1, Jan. 2005, pp. 254-260.
9. M.J. Akhbarizadeh, M. Nourani, D.S. Vijayasarathi, and P.T. Balsara, "PCAM: A Ternary CAM Optimized for Longest Prefix Matching Tasks", Proceedings of the IEEE International Conference on Computer Design, Oct. 2004, pp. 6-11.
10. Sergio R. Ramirez-Chavez, "Encoding Don't Cares in Static and Dynamic Content-Addressable Memories", IEEE Transactions on Circuits and System-II: Analog and Digital Signal Processing, Vol. 39, No. 8, Aug. 1992, pp. 575-578.
11. M. Nourani, D.S. Vijayasarathi and P.T. Balsara, "A Reconfigurable CAM Architecture for Network Search Engines", Proceedings of the IEEE International Conference on Computer Design (ICCD), 2006.
12. A. Alvandpour, R.K. Krishnamurthy, K. Soumyanath, and S.Y. Borkar, "A Sub-130-nm Conditional Keeper Technique", IEEE Journal of Solid-State Circuits, Vol. 37, No. 5, May 2002, pp. 633-638.
13. B. Yang, and L. Kim, "A Low-Power CAM Using Pulsed NAND-NOR Match-Line and Charge-Recycling Search-Line Driver", IEEE Journal of Solid-State Circuits, Vol. 40, No. 9, Aug. 2005, pp. 1736-1744.
14. K. Pagiamtzis and A. Sheikholeslami, "Content-Addressable Memory (CAM) Circuits and Architectures: A Tutorial and Survey", IEEE Journal of Solid-State Circuits, Vol.41, No.3, March 2006, pp. 712-727.