Design and testing of a high speed module based memory system

2009 IEEE 18th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS '09

Volumn , Issue , 2009, Pages 191-194

  Kollipara, Ravi ^a   Li, Ming ^a   Mullen, Don ^a   Beyene, Wendemagegnehu ^a   Madden, Chris ^a   Yuan, Chuck ^a   Kusamitsu, Hideki ^a,b   Ito, Toshiyasu ^a,b  

^a RAMBUS INC   (United States)

^b Yamaichi Electronics Co Ltd   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DATA RATES; HIGH SPEED MODULES; MEMORY SYSTEMS; MODULE-BASED;

ELECTRONICS PACKAGING;

EID: 74549148068     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EPEPS.2009.5338444     Document Type: Conference Paper

References (14)

1. "DDR3 SDRAM Specification," JEDEC Standard Document JESD79-3B, April 2008.
2. Joseph Fjelstad, Flexible Circuit Technology, Third Edition, BR Publishing, Inc. 2006.
3. H. Braunisch et al, "High-Speed Flex Circuit Chip-to-Chip Interconnects," IEEE Trans. on Advanced Packaging, vol. 31, No. 1 (2008), pp. 82-90.
4. K. Grundy et al. "Designing Scalable 10G Backplane Interconnect Systems Utilizing Advanced Verification Methodologies," 8-WP2, DesignCon2006, Santa Clara, CA.
5. R.T. Kollipara et al., "Evaluation of High Density LCP Based Flex Interconnect for Supporting >1 TB/s of Memory Bandwidth", 58th Electronic Components & Technology Conference, May 2008, Orlando, FL.
6. R.T. Kollipara et al., "Evaluation of a Module Based Memory System with an LCP Flex Interconnect", 59th Electronic Components & Technology Conference, May 2008, San Diego, CA.
7. Steven Woo, "Computing Trends And Applications Driving Memory Performance," Rambus Developer Forum, Tokyo, Japan, November 28, 2007.
8. K. Chang, et al., "A 16Gb/s/link, 64GB/s Bidirectional Asymmetric Memory Interface," Symposium on VLSI Circuits, Honolulu, HI, June 2008.
9. N. Nguyen, et al., "A 16-Gb/s Differential I/O Cell with 380fs RJ in an Emulated 40nm DRAM Process", Symposium on VLSI Circuits, Honolulu, HI, June 2008.
10. T. Wu, et al., "Clocking Circuits for a 16Gb/s Memory Interface," IEEE Custom Integrated Circuits Conference, San Jose, CA, September 2008.
11. W. T. Beyene, et al. "Design and Analysis of a TB/sec Memory System," Proceedings of IEEE 17th Topical Meeting on Electrical Performance of Electrical Packaging (EPEP), San Jose, CA, October, 2008.
12. W. T. Beyene, et al. "The Design and Signal Integrity Analysis of a TB/sec Memory System," DesignCon, Santa Clara, CA, February 2009.
13. W. T. Beyene et al., "Advanced modeling and accurate characterization of a 16 Gb/s memory interface," IEEE Trans. on Advanced Packaging, Vol. 32, No.2, pp. 437-659, May 2009.
14. V. Stojanovic, Channel Limited High-Speed Links: Modeling, Analysis and Design, PhD Thesis, Stanford University, 2004