A design methodology for domain-optimized power-efficient supercomputing

Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis, SC '09

Volumn , Issue , 2009, Pages

  Mohiyuddin, Marghoob ^a,b   Murphy, Mark ^a   Oliker, Leonid ^b   Shalf, John ^b   Wawrzynek, John ^a   Williams, Samuel ^b  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b LAWRENCE BERKELEY NATIONAL LABORATORY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ARCHITECTURE DESIGNS; BENCHMARK CODES; DESIGN CONSTRAINTS; DESIGN METHODOLOGY; HARDWARE/SOFTWARE; MATRIX; MATRIX MULTIPLICATION; MULTI-PROCESSORS; OPTIMAL CODES; PARAMETER SPACES; PEAK PERFORMANCE; PERFORMANCE POTENTIALS; POWER EFFICIENCY; POWER EFFICIENT; SCIENTIFIC COMPUTING; SOFTWARE AUTO-TUNING; SPACE EXPLORATIONS; SPARSE MATRIX-VECTOR MULTIPLICATION; SYSTEM DESIGN; TENSILICA; TIGHTLY-COUPLED; TRADITIONAL ARCHITECTURE;

CLOSED LOOP CONTROL SYSTEMS; COMPUTATIONAL EFFICIENCY; DESIGN; ENERGY EFFICIENCY; OPTIMAL SYSTEMS; PROGRAM COMPILERS; SPACE RESEARCH; TUNING; VECTOR SPACES;

MATRIX ALGEBRA;

EID: 74049161683     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1654059.1654072     Document Type: Conference Paper

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