A compiler-in-the-loop framework to explore Horizontally Partitioned Cache architectures

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2008, Pages 328-333

  Shrivastava, Aviral ^a   Issenin, Ilya ^b   Dutt, Nikil ^b  

^a AZ 85281   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARKING; COMPUTER AIDED DESIGN; DIGITAL INTEGRATED CIRCUITS; ENERGY POLICY; INDUSTRIAL ENGINEERING; LARGE SCALE SYSTEMS; PROGRAM COMPILERS; SPACE RESEARCH;

CACHE DESIGNS; DESIGN AUTOMATION CONFERENCE; DESIGN EXPLORATION; DESIGN PARAMETERS.; DESIGN SPACE EXPLORATION; DESIGN SPACES; ENERGY CONSUMPTION; ENERGY REDUCTIONS; ENERGY SAVINGS; EXHAUSTIVE EXPLORATION; HP IPAQ; MEMORY SUB SYSTEMS; MEMORY SUBSYSTEM ENERGY; MINIMUM ENERGY; PARTITIONED CACHE; SOUTH PACIFIC;

ENERGY CONSERVATION;

EID: 49549084782     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2008.4483968     Document Type: Conference Paper

References (21)

1. D. Burger and T. M. Austin. The simplescalar tool set, version 2.0. SIGARCH Comput. Archit. News, 25(3):13-25, 1997.
2. K. L. et al. H.263 test model simulation software. Telenor R&D, 1995.
3. K. Fan, N. Clark, M. Chu, K. V. Manjunath R. Ravindran, M. Smelyanskiy, and S. Mahlke. Systematic register bypass customization for application-specific processors. In Proc. of ASSAP, 2003.
4. A. Gonzalez, C. Aliagas, and M. Valero. A data cache with multiple caching strategies tuned to different types of locality. In ICS '95: Proceedings of the 9th international conference on Supercomputing, pages 338-347, New York, NY, USA, 1995. ACM Press.
5. M. R. Guthaus, J. S. Ringenberg, D. Ernst, T. M. Austin, T. Mudge, and R. B. Brown. MiBench: A free, commercially representative embedded benchmark suite. In IEEE Workshop in workload characterization, 2001.
6. Hewlett Packard, http://www..hp.com. HP iPAQ h4000 Series - System Specifications.
7. Intel Corporation, http://www.intel.com/design/pca/ applicationsprocessors/manuals/278693.htm. Intel PXA255 Processor: Developer's Manual.
8. Intel Corporation, http://www.intel.com/design/intelxscale/273473.htm. Intel XScale(R) Core: Developer's Manual.
9. Intel Corporation, http://www.intel.com/design/mobile/desguide/251012. htm. LV/ULV Mobile Intel Pentium III Processor-M and LV/ULV Mobile Intel Celeron Processor (0.13u) /Intel 440MX Chipset: Platform Design Guide, 2002.
10. IPC-D-317A Design Guidelines for Electronic Packaging Utilizing HighSpeed Techniques, 1995.
11. T. L. Johnson and W. mei W. Hwu. Run-time adaptive cache hierarchy management via reference analysis. In ISCA, pages 315-326, 1997.
12. H.-H. S. Lee and G. S. Tyson. Region-based caching: an energy-delay efficient memory architecture for embedded processors. In CASES '00: Proceedings of the 2000 international conference on Compilers, architecture, and synthesis for embedded systems, pages 120-127, New York, NY, USA, 2000. ACM Press.
13. M. Mamidipaka and N. Dutt. eCACTI: An enhanced power estimation model for on-chip caches. In Technical Report TR-04-28, CECS, UCI, 2004.
14. Micron Technology Inc., http://www.micron.com/products/drammobilesdram/. MICRON Mobile SDRAM MT48V8M32LF Datasheet, 2005.
15. J. A. Rivers, E. S. Tam, G. S. Tyson, E. S. Davidson, and M. Farrens. Utilizing reuse information in data cache management. In ICS '98: Proceedings of the 12th international conference on Supercomputing, pages 449-456, New York, NY, USA, 1998. ACM Press.
16. P. Shivakumar and N. Jouppi. Cacti 3.0: An integrated cache timing, power, and area model. In WRL Technical Report 2001/2, 2001.
17. A. Shrivastava, N. Dutt, A. Nicolau, and E. Earlie. Pbexplore: A framework for compiler-in-the-loop exploration of partial bypassing in embedded processors. In DATE '05: Proceedings of the conference on Design, Automation and Test in Europe, pages 1264-1269, Washington, DC, USA, 2005. IEEE Computer Society.
18. A. Shrivastava, I. Issenin, and N. Dutt. Compilation techniques for energy reduction in horizontally partitioned cache architectures. In CASES '05: Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems, pages 90-96, New York, NY, USA, 2005. ACM Press.
19. G. Tyson, M. Farrens, J. Matthews, and A. R. Pleszkun. A modified approach to data cache management. In MICRO 28: Proceedings of the 28th annual international symposium on Microarchitecture, pages 93-103, Los Alamitos, CA, USA, 1995. IEEE Computer Society Press.
20. O. S. Unsal, I. Koren, C. M. Krishna, and C. A. Moritz. The minimax cache: An energy-efficient framework for media processors. In HPCA '02: Proceedings of the Eighth International Symposium on High-Performance Computer Architecture (HPCA'02), page 131, Washington, DC, USA, 2002. IEEE Computer Society.
21. R. Xu and Z. Li. Using cache mapping to improve memory performance of handheld devices. Performance Analysis of Systems and Software, 2004 IEEE International Symposium on - ISPASS, pages 106-114, 2004.