Microarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI

IBM Journal of Research and Development

Volumn 51, Issue 5, 2007, Pages 529-543

  Flachs, Brian ^a   Asano, Shigehiro ^b   Dhong, Sang H ^a   Hofstee, H Peter ^a   Gervais, Gilles ^a   Kim, Roy ^a   Le, Tien ^a   Liu, Peichun ^a   Leenstra, Jens ^c   Liberty, John S ^a   Michael, Brad ^a   Oh, Hwa Joon ^a   Mueller, Silvia Melitta ^c   Takahashi, Osamu ^a   Hirairi, Koji ^d   Kawasumi, Atsushi ^b   Murakami, Hiroaki ^b   Noro, Hiromi ^e   Onishi, Shoji ^f   Pille, Juergen ^c   Silberman, Joel ^g   Yong, Suksoon ^a   Hatakeyama, Akiyuki ^h   Watanabe, Yukio ^b   Yano, Naoka ^b   Brokenshire, Daniel A ^a   Peyravian, Mohammad ^a   To, VanDung ^a   Iwata, Eiji ^h   more..

^a IBM   (United States)

^b TOSHIBA CORPORATION   (Japan)

^c IBM   (Germany)

^d SONY CORPORATION   (Japan)

^e Toshiba America Inc   (United States)

^f IBM JAPAN LTD   (Japan)

^g IBM T J WATSON RESEARCH CENTER   (United States)

^h Sony Computer Entertainment Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; PROGRAM PROCESSORS; STATIC RANDOM ACCESS STORAGE;

DYNAMIC CIRCUITS; MICROARCHITECTURE; MULTIPLE-DATA PROCESSOR; SYNERGISTIC PROCESSOR;

SILICON ON INSULATOR TECHNOLOGY;

EID: 35649007366     PISSN: 00188646     EISSN: 00188646     Source Type: Journal    
DOI: 10.1147/rd.515.0529     Document Type: Article

References (13)

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